System Modeling and Verification - Analog (ILV)

Studiengangssemester 3. Semester
Semesterwochenstunden / SWS2,0
ECTS Credits3,0
Unterrichtssprache Englisch

This course provides an introduction in methodologies and computer aided design tools needed for system level modelling and verification of analog and mixed-signal integrated circuits.

Prerequisite in attending this course is the successful completion of all lectures of the first and second semester ISCD as well as basic knowledge in VHDL, MATLAB, Simulink.

The course offers lectures in the analog design flow, discrete time modeling of analog blocks using tools like MATLAB and Simulink, the analog modeling language VHDL AMS as well as SystemC and SystemC AMS.

The lectures are accompanied by lab exercises.

- Ken Kundert, "Mixed Signal Design Flow", .

- Frevert et al., "Modeling and Simulation for RF, System Design", Springer, 2006.

- Herve, "VHDL-AMS Anwendungen und Industrieller Einsatz", Oldenbourg, Muenchen, 2006.

- Peter Asthenden, "The Designer's Guide to VHDL", Morgan Kaufmann Publishers Inc, 2002.

- Fraunhofer Institute for Integrated Circuits

"SystemC and SystemC-AMS for High Speed Serial Interfaces"


- "Analog and Mixed-Signal System Design Signal System Design with SystemC" , FDL'04 Tutorial, September 16, 2004

Considerable parts of this course will be spent on practical work in the EDV room with additional explanations and theoretical background given by the lecturers. Additional reading of literature has to be done at home to prepare for lectures and lab sessions.

Details on exams and grading are given by the lecturers in class.

Overall grading and weighting for all parts of the SysMod course is:

20% lecture / lab participation

25% homework and self-study

55% final exam