Digital Design with HDL (ILV)

Studiengangssemester 2. Semester
Semesterwochenstunden / SWS5,0
ECTS Credits7,5
Unterrichtssprache Englisch

Knowledge and basic experience in the design of digital integrated circuits using Hardware Description Languages (HDL), in particular using VHDL.

Prerequisites for this course are the completion of all courses of ISCD first semester, a working knowledge of VHDL (this course is not a VHDL lecture!) and a working knowledge of the digital tool flow at CUAS.

Lectures, labs and a project assignment offer information on the usage of Hardware Description Languages (HDL), on VHDL for synthesis and on HDL verification issues. Furthermore, low power design methods at the HDL level and Intellectual Property (IP) issues are discussed.

- Roth, "Digital Systems Design Using VHDL"

- Rushton, "VHDL for Logic Synthesis"

- Manuals, training material and application notes of CAD tools

The course includes lectures, homeworks and a project assignment. ll lectures are accompanied by practical work in lab.