System Modeling and Verification - Digital (ILV)

Studiengangssemester 2. Semester
Semesterwochenstunden / SWS3,0
ECTS Credits4,5
Unterrichtssprache Englisch

The students gain a basic knowledge on modeling of interated circuits, mainly on the system level. This includes the verification of models and circuits.

Prerequisites for this course are the completion of all courses of ISCD first semester, a working knowledge of VHDL (this course is not a VHDL basics lecture!) as well as basic knowledge in MATLAB, Simulink and a working knowledge of the digital tool flow at CUAS.

Lectures of this course provide information on system theory, chip level modeling and structural level modeling (RTL). Furthermore, verification on the chip and structural level is dicussed in detail. The practical aspects are provided in labs using various CAD tools (MATLAB Simulink, ...) for modeling and verification.

- Handouts are provided in class

Considerable parts of this course will be spent on practical work in the EDV room with additional explanations and theoretical background given by the lecturers. Additional reading of literature has to be done at home to prepare for lectures and lab sessions.