Testing of Integrated Circuits (ILV)

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LehrveranstaltungsleiterIn:

 Dongning Zhao , Ph.D.

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LV-NummerM-ISCD-3.01
LV-KürzelTEST
Studienplan2011
Studiengangssemester 3. Semester
LehrveranstaltungsmodusPräsenzveranstaltung
Semesterwochenstunden / SWS3,5
ECTS Credits4,5
Unterrichtssprache Englisch

This course provides knowledge in design for test as well as in testing of integrated circuits under production environment. Students will understand requirements that are necessary for the production test to achieve todays quality demands for analog and digital circuits.

Fundamentals of electrical engineering

Basic knowledge of electronic components

Basics in circuit design

Basic knowledge in the use of CAD Tools, the completion or parallel attendance of the course on CAD Tools is required for labs and projects of all courses in this module

Knowledge of VHDL and basic digital design flow with simulation (MODELSIM), synthesis (SYNOPSYS) is mandatory.

Lectures of this course provide information on the economic relevance of testing, failure rates, ATE and QA procedures. Furthermore, fault mechanism in integrated circuits, it's modeling, simulation and ATPG are discussed. Design for test (DFT) techniques, scan, BIST, CAD tools for fault simulation and ATPG are additional topics.

Practical lab works with design tools for simulation, synthesis and pattern generation give a basic understanding of EDA tools used to achieve design-for-test requirements.

Excursions to test departments of integrated circuit manufacturers are planned.

- M. Abramovici, "Digital Systems Testing and Testable Design"

- M. Bushnell, "Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits"

- Ian A. Grout: "Integrated Circuit Test Engineering", Springer.

- Alexander Miczo: "Digital Logic Testing and Simulation", Wiley Interscience.

- Miron Abramovici, Mevin A. Breuer, Arthur D. Friedman: "Digital System Testing and Testable Design", Wiley Interscience.

Lectures, homework, case studies and excursions to semiconductor test facilities

Final exam, homework, evaluation of case studies and excursion reports

LAB protocols, Homework, Examination