Monolithic CMOS System-on-Chip (SoC) design is reaching hard limits due to factors such as system complexity, manufacturing costs and yield, on-chip interconnect delays and other manufacturing constraints. A fast-growing trend that could solve most of these problems is now approaching, the “disaggregation” of SoCs. This means, that different SoC building blocks are separated as stand-alone dies, realized in cost- and performance-optimized integrated circuit (IC) technologies, called “chiplets”. The chiplets are reassembled or interconnected by a high-density System-in-Package (SiP) substrate such as Si-Interposer.

Chiplet integration requires power optimized, low cost and small area serial data links for chip-to-chip communication. Chiplet transceivers connect two chiplets through a high number of parallel data channels (up to 1000 and more). This requires new strategies for data synchronization, equalization, crosstalk cancellation and significant power reduction. Since the overall data rates required for chip-to-chip communication are increasing exponentially, the key performance metrics for chiplet communication interfaces are bandwidth density (how many bits of data can be transmitted through a given geometry in) and power efficiency (how much energy is required to transmit 1 bit of information).

The research objectives for the realization of optimized chiplet data transceivers in this project are as follows.

Research objective 1 – Full-duplex and single-ended chiplet transceiver architectures:
New transceiver architectures for improved bandwidth density (small area) and power efficiency will be investigated and realized in 28nm CMOS technology. To meet the stringent requirements, single-ended and full-duplex data transceivers will be researched, requiring optimized data equalization, modulation and echo cancellation strategies.

Research objective 2 – Data crosstalk cancellation:
Crosstalk between the metal lines of densely routed data buses has become a fundamental limitation to extending the bandwidth of next-generation single-ended chiplet buses. Research and implementation of active crosstalk cancellation circuits is the main focus of research objective 2.

Research objective 3 – Chiplet data channel design modeling and optimization:
Electromagnetic modeling and optimization of SiP data buses is an important prerequisite for RO1 and RO2. Not only the electromagnetic crosstalk between adjacent data channels, but also the crosstalk between data channels and sensitive on-chip structures such as RF building blocks on communication chips will be simulated and optimized.

For laboratory verification of the chiplet transceiver circuit concepts, two demonstrator testchips will be fabricated in TSMC 28nm CMOS technology using the Europractice mini@sic prototyping MPW runs. The testchips will be mounted on optimized SiP substrates with multi-channel data links and verified by lab measurements.