System Modeling and Verification - Analog (ILV)Back
DI (FH)Wolfgang Scherr
|Semester of degree program||Semester 3|
|Mode of delivery||Presencecourse|
|Language of instruction||English|
This course provides an introduction in methodologies and computer aided design tools needed for system level modelling and verification of analog and mixed-signal integrated circuits.
This course provides an introduction in methodologies and languages needed for design und system level modelling of analog integrated circuits. This course extends the digital modelling course.
Prerequisite in attending this course is the successful completion of all lectures of the first and second semester ISCD as well as basic knowledge in VHDL, MATLAB, Simulink.
Prerequisite in attending this course is the successful completion of all lectures of the first and second semester ISCD as well as basic knowledge in electronics design (like linear algebra basics, basic circuit elements, Kirchhoff laws and HDL languages like VHDL oder Verilog from the digital modelling course).
The course offers lectures in the analog design flow, discrete time modeling of analog blocks using tools like MATLAB and Simulink, the analog modeling language VHDL AMS as well as SystemC and SystemC AMS.
The lectures are accompanied by lab exercises.
The course provides a broad overview of analog modelling in chip design. It starts with basic macro modelling, continues with linear conservative and non-conservative modelling and ends with discrete time modelling. Languages introduced are SPICE, SystemC/SystemC-AMS, VHDL/VHDL-AMS and SystemVerilog/Verilog-A.
- Ken Kundert, "Mixed Signal Design Flow", .
- Frevert et al., "Modeling and Simulation for RF, System Design", Springer, 2006.
- Herve, "VHDL-AMS Anwendungen und Industrieller Einsatz", Oldenbourg, Muenchen, 2006.
- Peter Asthenden, "The Designer's Guide to VHDL", Morgan Kaufmann Publishers Inc, 2002.
- Fraunhofer Institute for Integrated Circuits http://www.eas.iis.fraunhofer.de/
"SystemC and SystemC-AMS for High Speed Serial Interfaces"
- "Analog and Mixed-Signal System Design Signal System Design with SystemC" , FDL'04 Tutorial, September 16, 2004
Available on request.
Considerable parts of this course will be spent on practical work in the EDV room with additional explanations and theoretical background given by the lecturers. Additional reading of literature has to be done at home to prepare for lectures and lab sessions.
Considerable parts of this course will be spent on practical work in the EDV room with additional explanations and theoretical background given by the lecturers. Additional reading of literature has to be done at home to prepare for lectures and to work through the lab sessions.
Details on exams and grading are given by the lecturers in class.Overall grading and weighting for all parts of the SysMod course is:20% lecture / lab participation25% homework and self-study55% final exam
Detailed evaluation data is available on request. Full presence in the lecture is required; homework and final exam must be positive each to pass this course.