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WS 2020
LehrveranstaltungTypSWSECTS-CreditsLV-Nummer
Design of Analog Integrated Circuits ILV 5,0 7,0 M-ISCD-1.04
SS 2020
LehrveranstaltungTypSWSECTS-CreditsLV-Nummer
Advanced Topics in Analog Integrated Circuits ILV 5,0 7,0 M-ISCD-2.01
TitelAutorJahr
Design of Digitally Controlled Oscillator for WLAN 802.11b/g Clock Synthesizer Darshan Bhaskar Shetty 2016
TitelAutorJahr
Design of Digitally Controlled Oscillator for WLAN 802.11b/g Clock Synthesizer Darshan Bhaskar Shetty 2016
TitelAutorJahr
Konferenzbeiträge
TitelAutorJahr
Dynamically Reconfigurable Multiband Subsampling Receiver Architecture in: 4th Workshop Radio Frequency Engineering Working Group of Austrian Research Association, 17-18 Oct 2016, VillachKale, A., Sankara, R., Pasupureddi, V., Sturm, J.2016

Konferenzbeiträge
TitelAutorJahr
Dynamically Reconfigurable Multiband Subsampling Receiver Architecture in: 4th Workshop Radio Frequency Engineering Working Group of Austrian Research Association, 17-18 Oct 2016, VillachKale, A., Sankara, R., Pasupureddi, V., Sturm, J.2016


Verwenden Sie für externe Referenzen auf das Profil von Ajinkya Kale folgenden Link: www.fh-kaernten.at/mitarbeiter-details?person=a.kale