System-on-Chip for Mobile Internet - IST-2000-30094

SoC-Mobinet is a project under IT framework 5, following action line IV.8.9 and carried out from 9/2001 to 12/2004. 

The objective of this project is to provide a European research and educational center to enhance the number of electronic engineers holding System-on-Chip skills required for mobile Internet applications. This project outlines a strategy and key building elements for a European research and education program in System-on-Chip focused on mobile Internet. The program is based on recognized center of excellence with a tight coupling of education, research and leading industrial manufacturers of wireless systems. Both activities are organized and run in close co-operation with European industrial players in the mobile internet market. The activities are twofold:

• To initiate joint R&D projects aimed at developing new classes of devices and gadgets required for the mobile Internet with special focus on methods of making the design flow more efficient, and
• provision of a European Center of Excellence for training in soc-ware for mobile Internet applications

The SoC-Mobinet consortium

• Royal Institute of Technology - Electronic System Design - Sweden (Coordinator)
• Carinthia Tech Institute - School of Electronics - Austria
• Tampere University of Technology - Digital and Computer Systems Laboratory - Finland
• Danmarks Tekniske Universitet - Department of Informatics and Mathematical Modeling
• University of Turku - Department of Applied Physics - Laboratory of Electronics and IT
• Infineon Technologies Microelectronic Design Centers Austria GmbH - Austria
• Spirea AB - Sweden
• ACREO AB - Sweden

Course material prepared under SoC-Mobinet

Visit SoC-Mobinet courseware pages

PhD and diploma theses carried out by CTI students and supported by SoC-Mobinet

• A. Albel, Entwurf von low-voltage differential Signal (LVDS) Pads für eine 0.18 micron CMOS Technologie: thesis in pdf
• A. De Vora, Design of a Configurable Speed Optimized Radix 4 Hardware Divider: thesis in pdf
• A. Hradetzky, Development of a Matlab Toolbox for Polyphase FIR Filters: thesis in pdf
• T. Gostner, The Design of a Current-Steering Digital to Analog Conerter DAC in 0.13 micron CMOS Technology: thesis in pdf
• A. Schilke, An Automatic Decoder Generator for a Scalable DSP Architecture: thesis in pdf
• C. Panis, High-level Language Programmable and Configurable DSP Core Concept for Future SoC Requirements
• M. Müller, Investigation, Simulation and Implementation of Hardware-Optimised Architectures for a Frequency Translation Unit in Software Radio Receivers
• M. Novak, System design (Matlab/C++) and FPGA/DSP – based rapid prototyping of core units for wireless software radio receivers and investigation and implementation of optimized programmable multi-rate filter architectures
• M. Parainer, Development of a debug interface for the programmable host interface-implementation of the IOM2 interface
• Liu Shih-Fu, Design and FPGA-implementation of a run-time re-programmable high performance multi-rate filter processor in VHDL and SystemC
• C. Scheichl, A Universal Run-time Re-configurable QAM-/QPSK-Frequency-Hopping Transmitter
• A. Machne, A Real-Time FPGA-Based IEEE802.11a Compliant OFDM - Baseband Transmitter / Receiver
• S. Albl, Design and FPGA-implementation of high performance IP-cores for wideband software radio communication
• F. Hus, Investigation and Design of a Highly Linear CMOS-buffer for Driving a High-Performance ADC

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