School of
Engineering & IT
Degree Program
Integrated Systems and Circuits Design
Master of Science in Engineering (MSc)
4 semesters
120 ECTS
limited study places
Full time
Tuition fee: € 363.36 per semester
Location: Villach
Language of instruction: English
SysMod - System Modelling and Verification ISCD-2.02
Course SysMod:
The 2nd semester course SysMod ( course number ISCD-2.02 ) provides an introduction in methodologies and computer aided design tools needed for system level modelling and verification for microelectronics design.
The whole SysMod course accounts for 7.5 ECTS credit points.
Teaching Method:
Considerable parts of this course will be spent on practical work in the EDV room with additional explanations and theoretical background given by the lecturers. Additional reading of literature has to be done at home to prepare for lectures and lab sessions.
Prerequisites:
Prerequisite in attending this course is the successful completion of all lectures of the first semester ISCD as well as basic knowledge in VHDL, Matlab, Simulink.
Responsible lecturers:
Eva Tatschl, Manfred Ley


