School of
Engineering & IT
Degree Program
Integrated Systems and Circuits Design
Master of Science in Engineering (MSc)
4 semesters
120 ECTS
limited study places
Full time
Tuition fee: € 363.36 per semester
Location: Villach
Language of instruction: English
Digital Design with HDL - selected topics
- Review of Hardware Description Languages
(motivation for using HDL's, available HDL's, coding rules, code checks) - VHDL design for synthesis
(design flow, synthesizeable VHDL, VHDL to hardware mapping, synthesis constraints) - Introduction to HDL verification
(definitions, verification methods) - Power saving methods
(high level methods on architecture and implementation level) - Intellectual property issues
(IP sources, IP quality issues, legal issues)


