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  • Integrated Systems and Circuits Design

    Master of Science in Engineering
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R & D - Research and Development in Microelectronics

Research and development work link the microelectronics group to national and international partners of both industry and academia. This keeps lecture contents up to date in the fast changing world of semiconductor industry and offers attractive project and thesis work to our students.

R&D work is carried out by permanent staff, PhD students as well as undergraduate students in course of diploma theses or internships.

The group is a competence center for VLSI signal processing, offering many years of experience in:

  • digital VLSI design
  • design of digital IP modules
  • IP integration using state of the art digital design flow
  • analog and mixed-signal VLSI design
  • design and integration of multi-rate filter processors into A/D and D/A interfaces
  • mixed-signal VLSI integration for optimal silicon utilization and low power
  • high performance analog and digital design with very deep sub-micron (vdsm) technologies
  • RF CMOS design (LNA, mixer, ...) using deep sub-micron technologies.

Research Projects

Figure 1:
Focus areas of proposed
Ressel center

Modern solutions of wireless RF systems require multi-standard multi-band functionality for future software defined radio and agile radio products. The high number of wireless standards implemented in mobile devices (GSM/EDGE, UMTS, LTE, Wi-Fi, GPS, Wireless HD, Wireless USB, NFC, DVB-S2, ….) with preferably single radio architectures creates a number of challenges which are not covered by “classical” RF-circuit design and analog-mixed signal design methodologies only.

A high number of challenges like strong interference between the different RF frontends, a complex interface between the RF integrated circuit, external components and the antenna, as well as limitations of available power, chip area, PCB area and mainly costs needs to be solved for future products.

This leads to the necessity of new RF frontend concepts leveraging reconfigurable building blocks using “digitally assisted RF” concepts to cope with non-idealities in the RF performance such as gain control, offset control or noise and crosstalk compensation. These concepts are already quite established in standard low-frequency analog design, while they were hardly used for RF applications in the past. Furthermore, there is strong signal interaction between RF, analog blocks, digital blocks on a system-on-chip (SoC) and external components on package and board level. This requires new multi-disciplinary design and modeling approaches, which are necessary to combine the diverse field of knowledge and tooling used for development of integrated RF systems.

The research activities of the proposed Ressel center at Fachhochschule Kärnten will focus on reconfigurable integrated radio-frequency (RF) systems and circuits based on standard integrated circuit CMOS technologies. Also electromagnetic interference and co-existence issues in modern wireless transceivers will be investigated and improved. The tasks include all necessary development steps like modeling, simulation, circuit implementation and lab characterization, supporting future integrated wireless communication systems.

The focus of proposed Ressel center is illustrated in Figure 1.

Agile RF Transceivers and Front-Ends for Future Smart Multi-Standard Communications Applications

  • Project Number: 270683-2
  • Project Website:
  • Project Start: 1st April 2011
  • Project Duration: 3 years
  • Total Project Costs: €40.934.495,-
  • Project Partners: 38, spread over 12 European countries

ARTEMOS is co-financed by ENIAC under work program 2010 SP2 (wireless communication) and national FFG funding.

Project summary

This project aims at developing architecture and technologies for implementing agile radio frequency (RF) transceiver capacities in future radio communication products. These new architecture and technologies will be able to manage multi-standard (multi-band, multi-data-rate, and multi-waveform) operation with high modularity, low-power consumption, high reliability, high integration, low costs, low PCB area, and low bill of material (BOM).
This will not just require smart RF architectures in advanced CMOS and BiCMOS technology, but also need incorporating of e.g. MEMS technologies and novel simulation methodology for achieving these complex optimizations.
Multi-standard multi-band terminals integrating all standards (e.g. GSM/EDGE, UMTS, LTE) and beyond that additional wireless communications systems for mobile devices (such as Wi-Fi, GPS, WirelessHD, WirelessUSB, NFC, PMR, all digital TV standards, etc.) in a single radio architecture with the lowest number of external SAW or BAW filters and power amplifiers. Frequency agile high dynamic range digital friendly RF architectures suitable for nanoscale (Bi)CMOS together with tuneable filters are the key innovations proposed for this project.
Today, the analog RF frontend simply duplicates the circuitry for each band. Due to the severe signal constraints in a cell phone and limitations of the current technologies and architectures, it is not possible to create an integrated solution.
A tunable RF frontend radio is required which can cover all bands and bandwidths in a range from 0.3GHz to 5GHz, meeting all specifications within a mobile device. This requires homogeneous or heterogeneous integration of a set of complete new tunable architectures and technologies (high-Q on-chip inductors, tunable MEMS capacitors, MEMS switches and resonators or tunable BAW/SAW filters and integrated passive devices processes) with existing (Bi)CMOS technologies.
The complexity requires new advancements in the simulation techniques and modelling aspects to enable these multiple new technologies.
The ARTEMOS project has a large consortium of 38 partners spread over 12 countries, including all major European players in wireless communication.

Task of Carinthia University of Applied Sciences

To fulfill the requirements of multi-standard wireless systems, new transceiver key building blocks needs to be developed, enabling a high flexibility with improved re-configurability and digital assistance. The CUAS microelectronic department is working on the development of re-configurable CMOS RF wide-band LNA’s including automatic gain control and programmable band-pass filter characteristics using mixed signal enhancement techniques. This will reduce the number of parallel RF receive paths in next generation wireless devices as shown in Figure 1. The development is based on standard CMOS technologies enabling highly integrated SOC solutions.

Figure 1:
Block diagram of an integrated color sensor

Integrated Color Sensor in CMOS Technology

  • Project Start: 1st April 2011
  • Project Duration: 2 years
  • Project Partners:Infineon Technologies Austria AG
  • University of Ljubljana
  • COSMOS is funded by the FFG FIT-IT Program

Project summary

The COSMOS project is set out to research a novel monolithically integrated low-cost color sensor, based on standard CMOS technology without costly process modifications or any external color filter structure. It will therefore technologically out beats the current integrated solutions and is fully compatible with mass market applications. The sensor is based on a radical new photodiode color sensing technology in combination with new algorithms for color reconstruction. It will include a high dynamic range analog frontend with a minimum of 20bit resolution optimized for low-power and minimum area, which is a mandatory requirement for focused SOC applications. Research on new analog-to-digital converter architectures to fulfill the stringent requirements out-performing low-cost state-of-the-art solutions is a mandatory project task. A fully integrated color sensor prototype system will be realized as key enabler for scientific and technical exploitations.

Task of Carinthia University of Applied Sciences

- Task 1:
CUAS is working on the development of integrated color detectors, based on process and devices simulations with Synopsis TCAD development tool. The new detector structures are implemented in a standard CMOS technology and the performance will be analyzed by 2½- and 3-dimensional field simulations including optical carrier excitation.

- Task 2:
This task covers modeling of the color detector for Matlab system level simulations and circuit simulations. The necessary algorithms for color reconstructions of the incoming light will be developed and verified with Matlab. The hardware implementation will be done in standard CMOS technology and optionally in FPGA for evaluation.

- Task 3:
The digital signal processing concept for ADC data (decimation, filtering) will be defined and implemented.

- Task 4:
The lab evaluation hardware for accurate characterization of integrated color sensors will be developed. The optical lab setup will be used for characterization of the developed color detectors and fully integrated sensors including ADC.

ADC for Deep Submicron Technologies - ARDES

High volume SoC solutions for wireless and wireline communication solutions must move to deep sub micron technologies to remain competitive. Higher bandwidth, lower power consumption and more features are requested by the customers. ARDES targets the xDSL and mobile handset markets, together they are expected to see revenue of more than 55 Billion USD in 2007. Moving mixed signal devices to deep sub micron technologies is one of the biggest challenges facing SoC and SiP designers today. The economic advantages for the first movers are expected to be huge as it will allow for a host of new features on the consumer side and will reduce complexity, power consumption and overall costs on the provider side. The ARDES project team will tackle the problem of analog to digital conversion in deep sub micron CMOS. These components are key enablers for communications SoC's and SiP solutions. The results of ARDES will give a significant advantage compared to existing solutions, allowing it to offer less expensive, more power efficient solutions with greater flexibility and shorter time to market.


The project ARDES was started in January 2008 and will have a duration of 2 years. It is a cooperation with

  • Infineon Technologies Austria AG
  • Carlos III University - UC3M

Carinthia University of Applied Sciences will contribute with modeling, design and implementation of high-speed digital blocks. Furthermore an evaluation platform will be developed. The project is funded by Fit-IT and industrial partners.

Mobile Multicast Receiver - M2RX

Feature-rich mobile handsets are the utmost market desire. The M²RX project will boost and extent the functionality of future mobile equipment by providing SoC concepts and solutions for upcoming broadcast and multicast services (e.g. TV, distance learning, civil protection, ...) and combining them with existing systems (UMTS, GPRS, GSM, etc.). To meet this challenging goal novel circuit and system concepts need to be created by using advanced semiconductor technologies. They shall enable new applications in the area of mobile communication. Thus, low cost, low features size and energy efficiency are of utmost importance to enable future products for the mass market. This will enable a number of new mobile  applications in the portable, battery-operated, energy efficient, low cost and mobile digital environment. Enabling broadcast or multi cast technology, allows much more information flow to the end user than point-to-point connections such as GSM or UMTS.


The project M2RX was started in February 2008 and will have a duration of 2 years. It is a cooperation with

  • Infineon Technologies Austria AG
  • DICE GmbH & Co KG
  • TU Vienna - Institute for Electrical Measurement and Circuit Design
  • Johannes Kepler University Linz - ICIE

Carinthia University of Applied Sciences will contribute with CMOS RF design for LNA and mixer circuits including concepts for automatic gain control. Furthermore an evaluation platform will be developed. The project is funded by Fit-IT and industrial partners.

System-on-Chip for Portable Audio - SOCPOD

Today's multimedia applications use a huge variety of high performance integrated components (off-the-shelf components and digital processors). They realize digital processing functions like encoding or decoding of video or audio streams (processor cores and software), digital interfaces (USB, 2-wire, flash memory, etc.), analog interfaces (analog-to-digital converters – ADCs and digital-to-analog converters – DACs for video as well as audio signals) and power management functions (handling a variety of supply voltages). While highest quality in video and audio performance was the main design criteria for long time, a new generation of multimedia products evolved over the recent years. The availability of video and audio virtually everywhere, independent from mains supply, has become a major trend and a huge market for suppliers. Now, portable multimedia products have dramatically changed the metrics of the required components. Space and battery life time have become of major concern to the designers, eventually even compromising the performance.

These design issues can only be solved by increasing the integration level, combining most, if not all, multimedia functions on a single integrated circuit (System-on-Chip SoC, System-in-Package SiP). Most advanced fabrication technology is required and the challenge of the designers is not only found in the tremendous design complexity, but also in the integration of critical analog and mixed-signal functions, as described above.

Project socPod addresses these problems for portable audio products and research in new analog interfaces, especially oversampled audio ADCs and DACs. Oversampled data-converters, well suited for SoC integration, are adapted to advanced fabrication technologies as well as reduced supply voltages and lowest power consumption, while still delivering a target performance of 93-95 dB SNR. This is done by a global optimization at system, architecture and circuit level of the signal path from anti-aliasing filter via noise shaper, decimation and interpolation filters to equalizer and smoothing filter.

socPod is a Cooperation between

Project Duration

1.9.2006 - 30.9.2009

Contribution of Carinthia University of Applied Sciences

Carinthia University of Applied Sciences designed and implemented selected structures for digital signal processing functions. Special architectures and circuits for low power decimation and interpolation filters, parametric equalizers and arithmetic units for software programmable DSP cores were developed and, where required, also fabricated on a testchip. Compared to conventional structures, the power consumption could be reduced up to 75%.

Mask Layout of CIC Filter Unit


  • Yingwei Wang, Chi Zhang, Erwin Ofner, Lucas Groposo: "Third Order Delta Sigma Modulator for Portable Audio", in Proceedings of Austrochip 2010, Oct. 2010, Villach, pp79-82, ISBN 978-3-200-01945-4.
  • Erwin Ofner, Chi Zhang, Haifeng Zhou: "Integration of Low-Power Decimation Filters", 3. Forschungsforum der österreichischen Fachhochschulen, April 2009, Villach, pp147-151, ISBN 978-3-853912850.
  • Haifeng Zhou, Chi Zhang, Erwin Ofner: "Low-Power Decimation Filter for Portable Audio Applications", in Proceedings of Austrochip 2008 in Linz, Oct 2008, pp48-51, ISBN 987-3-200-01330-8.
  • Stephen T. Burgess, Erwin Ofner: "Recursive All-Pass Interpolation Filters for Digital Audio Applications", in Proceedings of Austrochip 2008 in Linz, Oct 2008, pp52-55, ISBN 987-3-200-01330-8.


Master Theses

  • Shanmukha Reddy Mandha: CORDIC Based Equalizer Coefficients Calculation Unit
  • Stephen Burgess: Recursive All-Pass Filters for Efficient Interpolation of Discrete Time Audio Signals
  • Haifeng Zhou: The Low Power Design and the VLSI Implementation of a Decimation Filter for an Over-sampled Data Converter

The project was funded by the FIT-IT program of the Austrian Research Promotion Agency (FFG) and the industrial partner.

The author of this page is not responsible for the contents of any links given

SoC for Advanced Multimedia Broadband Access

In order to measure up to the development of shorter time-to-market cycles on the one hand and technical requirements of more complex SoC designs on the other, a new architectural approach is needed. This new approach not only enables design-reuse and early error detection but also offers a surface- and cost optimized solution. It is therefore imperative to conduct projects in a time span of as short as six months from initial specification to the final and correct implementation; regardless of the complexity of design problems. Approaches such as Multi DSP architectures or FPGA solutions do offer the required flexibility, but they are not optimal when it comes to performance and costs per piece. For this reason they are hardly ever applied in the mass market of consumer electronics.

SAMBA is designed to meet up to the market requirements for a cost-optimized programmable multi-standard solution. Because of constantly rising initial production costs there is also a demand for growing sales figures for a Return on Investment.

SAMBA combines the different technical requirements, which will allow scalability of the processing power, programmability and an optimal weighting of hardware- and software-based designs in order to find an optimal balance between fixed-wired and freely-programmable modules. The SAMBA core works on a high-grade parallel and scalable VLIW processor architecture that was developed by ON DEMAND Microelectronics and which should be optimized for special processing operations. It has to be guaranteed that internally- developed hardware modules as well as IPs made by other manufacturers can be seamlessly integrated into the platform and the simulation environment.

With the platform SAMBA a generally valid method should be established within this project so that such hardware/software requirements can be simulated. The suitability of this method is indicated by a multimode receiver for the highly contrarily-working standards DVB-T and ATSC. With SAMBA fixed-wired single-standard solutions as well as flexible software-programmable multi-standard solutions for low-cost and high-end SoC should be conceptualized and developed.

Project SAMBA is a cooperation between

  • ON DEMAND Microelectronics GmbH as industrial partner
  • the Institut of Computer Engineering at Vienna University of Technology
  • the School of Electronics of Carinthia University of Applied Sciences

The project was started in October 2005 with a duration of 2 years. Carinthia University of Applied Sciences contributed to this project with a study on the multi-mode demodulator frontend. The project was funded by FIT-IT and the industrial partner.

The author of this page is not responsible for the contents of any links given

A testchip with the propotype configurable
decimation filter was developed by CTI and
fabricated at austriamicrosystems

Multi-Mode Sigma-Delta Analog-to-Digital Converters for 3rd Generation Mobile Phones

The next generation of mobile communication will require parallel operation of, or at least, fast switching between different mobile phone standards like GSM and UMTS, W-CDMA. While this will lead to a drastic increase in complexity of the mobile terminal, it must not result in additional space (size of mobile equipment) or power dissipation (talk and standby times). These parameters are even expected to further improve.

Design and production of today's cellular phones is feasible only through system level integration and the availability of advanced manufacturing technologies. Modern cellular phones consist of three major integrated circuits (ICs) – the RF component, which amplifies the received antenna signal, the baseband and audio IC, which demodulates the received antenna signal and converts it into speech, audio, or data signals, and the power management IC, generating and managing all power sources required by the cellular phone. A key component in the receiver data-path is the analog to digital converter (ADC) – which converts the analog signal arriving from the antenna to a digital signal, which is much better suited for the subsequent processing. This ADC is usually placed in the baseband and audio IC. In the course of the project MMADC, a prototype of a configurable ADC for GSM and UMTS mode is developed. The work is focused on two major goals:

The configurable ADC consists of a sigma-delta modulator and a decimation processor. This architecture allows fast switching between GSM and UMTS mode. Big differences in technical requirements for GSM and UMTS required parallel integration of ADCs, resulting in larger chip area (higher production costs) and higher power consumption.

The second goal is the integration of the ADC into the power management IC. The baseband and audio IC mainly consists of digital building blocks – plus a few, however, very critical analog building blocks like the baseband ADC. Upcoming manufacturing technologies with feature sizes of 90nm and below are of course well suited for digital circuits, however, the critical analog modules will suffer from this evolution and encourage the move of the ADC into the power management IC. Due to higher supply voltages, this component requires larger transistor structures and is therefore better suited for the ADC integration.

The project MMADC is a cooperation between

The project was started in March 2004 and completed in June 2006. The project results will be adapted for integration into a real product by the industrial partner. The financial support through FIT-IT allowed the exploitation of ongoing research work, carried out by PhD students at both academic partners, for the development of this ADC prototype.


The author of this page is not responsible for the contents of any links given

TTA - Time Triggered Architecture


The AS8202 is a single chip communication controller for the Time Triggered Protocol ( TTP/C ).

TTP/C is an emerging communication protocol for fault-tolerant real time systems based on the Time Triggered Architecture. The application domain of this architecture is safety-critical by-wire systems in the automotive, aerospace and railway industries.

Basic work was done by the Vienna University of Technology in the ESPRIT OMI project "TTA" which resulted in the first silicon implementation of TTP/C, the prototype chip TTA-C1.

The microelectronics department of the Carinthia Tech Institute designed a functionally improved industrial single chip version of the communication controller, the TTP/C-C2 / AS8202.

Key improvements to the prototype chip are:

  • Meets automotive industrial specifications
  • New 0.35µ Flash-CMOS technology
  • Doubled speed on half silicon area
  • Integrated Flash memory 32 kbyte
  • Fast SRAM block 8 kbyte
  • Two independent FIFO-buffered communication channels
  • Asynchronous data rate up to 5 MBit/s
  • Synchronous data rate 25 MBit/s
  • Additional hardware to check data integrity
  • On-chip PLL clock generation
  • Additional testing circuitry

Background information to the Time Triggered Architecture and its applications can be found on:

TTP drive-by-wire:
protocol overview and application article ( german ).

a place to exchange information with other TTP users.

TTP/C specification, tools, hardware and software for TTA based applications.

TTP is a registered trademark of FTS Ges.m.b.H. and the TTTech logo is a trademark of TTTech Computertechnik AG. All other trademarks are the property of their respective holders.

The Time-Triggered Technology is protected by several granted or pending patents in the U.S., Europe and Asia.

The author of this page is not responsible for the contents of any links given

EMS - Embedded Microelectronic Systems

Embedded microelectronic systems are complex, integrated circuits consisting of analog and digital interfaces, signal processing modules with digital filters, DSP cores, controller cores and hard-wired modules for time critical tasks.

EMS goal is to build up competence in this field by carrying out various projects. EMS work is carried out from 1.10.2001 till 30.9.2004 and funded by bmvit and industry.

Major EMS Project Activities of the Microelectronics Group:    

One major activity concentrated on the development of Matlab toolbox functions for the design and implementation of digital multi-rate filters. This work is partly funded by SoC-Mobinet. Major activities are:

  • OPTIMIST-FIR, a student project carried out in 2000/2001. OPTIMIST stands for Optimized Implementation of Bit-level Structures.
  • OPTIMIST-Biquad, in this project the Matlab toolbox is further enhanced with cascaded biquads.
  • Design and implementation of various multi-rate decimation and interpolation filters.
  • OPTIMIST-Polyphase, a project to extend the Matlab toolbox developed in OPTIMIST-FIR for the implementation of poly-phase FIR structures (internship and diploma thesis).
  • Development of script-based design flow for multirate decimation and interpolation filters.

Other microelectronics activities in the field of digital and mixed-signal VLSI design are:

  • Design of a configurable CORDIC processor (diploma thesis).
  • Full custom VLSI design of a parallel multiplier module.
  • Feasibility study for the integration of a floating point multiply and accumulate (MAC) unit.
  • Design and implementation of an integrated temperature sensor (project POSITIV). This project started as student project (2002/2003) and continued as internship and diploma thesis (2003/2004).

The author of this page is not responsible for the contents of any links given here.

System-on-Chip for Mobile Internet - IST-2000-30094

SoC-Mobinet is a project under IT framework 5, following action line IV.8.9 and carried out from 9/2001 to 12/2004. 

The objective of this project is to provide a European research and educational center to enhance the number of electronic engineers holding System-on-Chip skills required for mobile Internet applications. This project outlines a strategy and key building elements for a European research and education program in System-on-Chip focused on mobile Internet. The program is based on recognized center of excellence with a tight coupling of education, research and leading industrial manufacturers of wireless systems. Both activities are organized and run in close co-operation with European industrial players in the mobile internet market. The activities are twofold:

  • To initiate joint R&D projects aimed at developing new classes of devices and gadgets required for the mobile Internet with special focus on methods of making the design flow more efficient, and
  • provision of a European Center of Excellence for training in soc-ware for mobile Internet applications

The SoC-Mobinet consortium

  • Royal Institute of Technology - Electronic System Design - Sweden (Coordinator)
  • Carinthia Tech Institute - School of Electronics - Austria
  • Tampere University of Technology - Digital and Computer Systems Laboratory - Finland
  • Danmarks Tekniske Universitet - Department of Informatics and Mathematical Modeling
  • University of Turku - Department of Applied Physics - Laboratory of Electronics and IT
  • Infineon Technologies Microelectronic Design Centers Austria GmbH - Austria
  • Spirea AB - Sweden
  • ACREO AB - Sweden

Course material prepared under SoC-Mobinet

Visit SoC-Mobinet courseware pages

PhD and diploma theses carried out by CTI students and supported by SoC-Mobinet

  • A. Albel, Entwurf von low-voltage differential Signal (LVDS) Pads für eine 0.18 micron CMOS Technologie: thesis in pdf
  • A. De Vora, Design of a Configurable Speed Optimized Radix 4 Hardware Divider: thesis in pdf
  • A. Hradetzky, Development of a Matlab Toolbox for Polyphase FIR Filters: thesis in pdf
  • T. Gostner, The Design of a Current-Steering Digital to Analog Conerter DAC in 0.13 micron CMOS Technology: thesis in pdf
  • A. Schilke, An Automatic Decoder Generator for a Scalable DSP Architecture: thesis in pdf
  • C. Panis, High-level Language Programmable and Configurable DSP Core Concept for Future SoC Requirements
  • M. Müller, Investigation, Simulation and Implementation of Hardware-Optimised Architectures for a Frequency Translation Unit in Software Radio Receivers
  • M. Novak, System design (Matlab/C++) and FPGA/DSP – based rapid prototyping of core units for wireless software radio receivers and investigation and implementation of optimized programmable multi-rate filter architectures
  • M. Parainer, Development of a debug interface for the programmable host interface-implementation of the IOM2 interface
  • Liu Shih-Fu, Design and FPGA-implementation of a run-time re-programmable high performance multi-rate filter processor in VHDL and SystemC
  • C. Scheichl, A Universal Run-time Re-configurable QAM-/QPSK-Frequency-Hopping Transmitter
  • A. Machne, A Real-Time FPGA-Based IEEE802.11a Compliant OFDM - Baseband Transmitter / Receiver
  • S. Albl, Design and FPGA-implementation of high performance IP-cores for wideband software radio communication
  • F. Hus, Investigation and Design of a Highly Linear CMOS-buffer for Driving a High-Performance ADC

The author of this page is not responsible for the contents of any links given here.

Technology Transfer

Research results are often used in cooperations with industry. An example is the Advanced Audio Decoder AS3520, available from austriamicrosystems. The component integrates a digital audio decoder (MP3, AAC and other formats as future option), a micro controller unit, data interfaces and the analog audio channels for reproduction of digital audio. The interpolation filter for the high performance 18 bit digital to analog converter was contributed by Carinthia Tech Institute.

Additional information: austriamicrosystems