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  • Integrated Systems and Circuits Design

    Master of Science in Engineering
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Selected Publications

Drago Strle, Uroš Nahtigal, Graciele Batistell, Vincent Chi Zhang, Erwin Ofner, Andrea Fant, Johannes Sturm, Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology, MDPI Sensors, Vol. 15, Issue 7, pp. 17786-17807, July 2015.

This article presents a color light detection system integrated in 130nm CMOS technology. The sensors and corresponding electronics  detect the light in CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. High resolution, hybrid, ∑∆ ADC converts each photo diode’s current into 22 bits digital result, canceling dark current of the photo diodes. Digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with transformation matrix, where the coefficients are extracted by training in combination with pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22 bits accuracy, consumes less than 60uA on average at 10 readings per second, and occupies approx. 0.8mm2 of silicon area including 3 photodiodes and analog part of the ADC. The DSP is currently implemented on FPGA.

 

J. Sturm, S. Popuri, X. Xiang, A 65 nm CMOS resistive feedback noise canceling LNA with tunable bandpass from 4.6 to 5.8 GHz, Analog Integr. Circuits Signal Process., Springer, in print.

Two low-noise amplifiers (LNA) with single ended input and differential output (balun) for multi-standard wireless receivers up to 6 GHz are presented. The proposed LNA’s are based on resistive-feedback concept, which enables wide-band input impedance matching and gain. A measured test structure of the first LNA shows a wide-band gain of 22 dB in a band of 0.2–5 GHz. Due to different noise cancellation techniques, the proposed LNA achieves a superior low noise figure (NF) of 1.7 dB at 2.5 GHZ. The IIP3 linearity and 1 dB compression point of the LNA are about −4 and −16.1 dBm at 2 GHz respectively. To relax external RF filters and LNA linearity requirements, a second LNA version with an on-chip LC bandpass load enabling a tunable center frequency from 4.6 to 5.8 GHz is presented. The LNA achieves a measured gain up to 30 dB and an IIP3 linearity between −6.5 and −10.3 dBm. The NF reaches a low value of 1.6 dB in the band of interest. Both LNA circuits are implemented in 65 nm CMOS technology with an active chip area of 112 × 78 and 154 × 197μm respectively. Therefore the proposed LNA structures are a cost-effective alternative to source degeneration based narrow-band LNA’s with comparable performance. Since wide-band input impedance matching is employed, the LNA’s can be used in re-configurable multi-standard wireless low-cost applications.

 

E. Ofner, V.C. Zhang, M. Ley: “Multirate Filter Design and Implementation for Mixed-Signal ICs“, in e&i Elektrotechnik und Informationstechnik ISSN 0932-383X, DOI 10.10077s00502-015-0313-6, pp262-268, 2015.

This paper describes the design of multirate filters used for the sample rate reduction of digital signals and their implementation on mixed signal integrated circuits. Reaching target specifications of power, speed and silicon area as well as realizing multimode operation presents challenges. Possible solutions are discussed particularly for those filter stages which operate at the high sample rates and illustrated in examples.

J. Sturm, M. Groinig, X. Xiang, Tunable Balun Low-Noise Amplifier in 65nm CMOS Technology, Radioengineering, Vol. 23, No. 1, pp. 319-327, April 2014.

The presented paper includes the design and implementation of a 65 nm CMOS low-noise amplifier (LNA) based on inductive source degeneration. The amplifier is realized with an active balun enabling a single-ended input which is an important requirement for low-cost system on chip implementations. The LNA has a tunable bandpass characteristic from 4.7 GHz up to 5.6 GHz and a continuously tunable gain from 20 dB down to 2 dB, which enables the required flexibility for multi-standard, multi-band receiver architectures. The gain and band tuning is realized with an optimized tunable active resistor in parallel to a tunable L-C tank amplifier load. The amplifier achieves an IIP3 linearity of -8 dBm and a noise figure of 2.7 dB at the highest gain and frequency setting with a low power consumption of 10mW. The high flexibility of the proposed LNA structure together with the overall good performance make it well suited for future multi-standard low-cost receiver front-ends.

 

G. Batistell, V.C. Zhang, J. Sturm, Color recognition sensor in standard CMOS technology. Solid State Electronics, Vol. 102, pp. 59-68, 2014.

Two integrated color detectors are presented as a solution for low cost color sensing applications. The color detection is based on lateral carrier diffusion and wavelength-dependent absorption-depth.

The proposed detectors are implemented in a standard 130 nm CMOS technology without process modification or color filters. Three independent output signals are obtained with spectral responsivities optimized to short, middle and long wavelengths. R, G, B or X, Y, Z standard color representation can be realized by a linear transformation of the output signals.

 

J. Sturm, G. Batistell, L.M. Faller, V.C. Zhang, Integrated CMOS Optical Sensor for Light Spectral Analysis, IEEE J. Sel. Topics Quantum Electron., Vol. 20, Issue: 6, Nov. 2014.

In this paper, a fully integrated photo sensor in standard CMOS technology is reported, which enables light spectral analysis in the visible light range without additional optical components like color filters or gratings. The proposed sensor structure provides a continuously tunable spectral responsivity based on lateral carrier diffusion effects in combination with tunable field electrodes for defined carrier redirection. The tunable responsivity characteristics in combination with digital signal processing can

be deployed for light spectral analysis like color measurements or full light spectral reconstruction. The realization of an accurate photometric color measurement based on the CIE X, Y, Z or R, G, B standard will be presented as an example for a basic light spectral analysis. Furthermore, the sensor application in a basic spectrophotometer is presented, providing a unique opportunity to realize a highly integrated low-cost spectrophotometer for basic spectral light measurements using a low-cost standard CMOS technology without process modification.

 

J. Sturm, G. Batistell, Highly Integrated Low-Cost Color Sensors, Proc. 8. Forschungsforum der österreichischen Fachhochschulen, April 2014, ISBN: 978-3-9503491-9-1

For light color measurement, the human eye color perception needs to be considered and realized in sensor devices. In this paper different sensor concepts for color recognition will be compared. A new innovative sensor solution will be presented, realized in CMOS integrated circuit technology, which enables light color analysis without any optical components like filters, lenses or gratings. The proposed sensor is based on vertically and laterally arranged photodiode structures, using lateral carrier diffusion and wavelength dependent light absorption for color discrimination. The structure was realized in a 130nm CMOS technology. The development is based on finite-element process and device simulations. Three independent sensor responses with optimized spectral responsivities allow the extraction of standardized R,G,B or X,Y,Z color information by dedicated signal processing. The proposed color detector is a highly integrated low-cost alternative for various color sensing applications.

 

G. Batistell, J. Sturm, A. Fant, D. Strle, Color Sensor for Ambient Light Measurements in 130nm CMOS Technology, Proc. 50th Conference on Microelectronics, Devices and Materials (MIDEM), 2014

For ambient light measurements, the spectral sensitivity of the human eye perception of brightness needs to be measured. This spectral sensitivity is modeled in the CIE luminosity function. For an ambient light measurement, a XYZ color sensor can be used, since the luminosity is inherently included as the Y component in the CIE XYZ color representation.

In this paper, the development of an integrated color sensor is reported. The proposed sensor structure consists of a set of laterally arranged integrated photodiodes, which are partly covered by metal. Color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. The sensor is implemented in 130nm CMOS technology. The proposed color detector structure and its principle of operation will be presented, together with FEM based device and process simulations of the sensor structure, including spectral light response. The simulations are based on Synopsys TCAD tools. Furthermore, a prototype color sensor testchip including measurement results will be reported.

To realize a normalized XYZ sensor response, a linear transformation of the sensor output is used. The transformation matrix can be extracted by a training strategy in combination with a pseudo-inverse operation for least-mean square approximation.

The proposed sensor structure is an improved version of the sensor presented in MIDEM 2013 conference [1] and is optimized for an on-chip CMOS integration together with a sigma-delta ADC and digital signal processing for color transformation.

 

V. C. Zhang, E. Ofner, Dušan Raič, J. Sturm, A. Fant, D. Strle, Decimation Filter and Tri-stimulus Colour Transformation for Ambient Colour Light Sensor, Proc. 50th Conference on Microelectronics, Devices and Materials (MIDEM), 2014

In this paper, a design of a DSP (digital signal processing) for an ambient colour light sensor is presented. It is currently implemented on Xilinx Virtex-5 FPGA evaluation board, but will be later on implemented on chip. It includes digital control part of the AFE (Analog Front End), decimation filter, offset and dark current cancellation circuits and tri-stimulus colour transformation algorithm. The design is used to evaluate the ambient colour light sensor [1] and the AFE including the SD ADC and serves as a test bench for further design improvements of integrated colour light sensor system. Different decimation filter structures for sigma-delta ADC colour sensor read out are evaluated in accordance with the ADC specifications of 4th order averaging filter, 2048Ms/s sample rate, 512 decimation factor, 4ks/s output sample rate and 24-bit output word length. A moving average filter is used to cancel the offset and dark currents of the photo-diodes. Digital control and circuits are designed for SD ADC and complete AFE testing purposes, generation of signals for high frequency chopping, low frequency chopping, dithering and multiplexing of different photodiodes. The 24-bit ADC output data is used to generate the digital representation of the photo currents by multiplying the data by the transformation matrix, which is calculated from the XYZ color matching function. Different truncation methods for three color signal branches and different structures have been simulated and compared. The results of complete sensing system are presented at the end.

 

S. Popuri, J. Sturm, A Wideband Resistive Feedback Balun LNA in 65 nm CMOS Technology, Proc. 22nd Austrochip Conference, pp. 59-62, 2014.

A wideband resistive feedback balun low noise amplifier (LNA) is presented in this paper. The proposed LNA has a wide band gain of 22 dB in a band of 0.2 - 5 GHz. An improved input balun stage is used to realize a single-ended to differential conversion with optimized transconductance and amplifier open loop gain. The wide band LNA is implemented in 65nm CMOS technology and has an area of about 0:009mm2. The power consumption is below 16mW at 1.2V single supply. Due to different noise cancellation techniques employed, the proposed LNA achieves a superior low noise figure (NF) of 1.7 dB at 2.5 GHZ. The IIP3 linearity and 1 dB compression point of the LNA are about 4dBm and -16.1dBm at 2 GHz respectively. The achieved performance results make the proposed LNA a competitive solution for RF applications up to 5GHz.

 

J. Sturm, Monolithic Integrated Color Sensor in CMOS Nano Technologies, Proc. Int. Conference on functional Integrated Nanosystems – nanoFIS, Graz, 2014.

Due to a huge market growth of optoelectronic applications like CMOS imaging sensors, solid-state LED lighting or bio-medical optical sensing, efficient methods for integrated, low-cost photometric color sensors gets more and more essential. Integrated color sensors are classically realized as Bayer Color Filter Arrays (CFA) or filter-less sensors based on stacked photodiodes like the Foveon X3 technology. These methods usually suffer from increased production complexity and costs. The proposed solution is a monolithic integrated sensor in an IC technology, which enables low-cost system-on-chip products in combination with extensive on-chip signal processing.

 

J. Sturm, S. Popuri, X. Xiang, CMOS Noise Canceling Balun LNA with Tunable Bandpass from 4.6 GHz to 5.8 GHz, Proc. 21st IEEE International Conference on Electronics Circuits and Systems, Marseille, 2014.

A compact resistive-feedback low-noise amplifier (LNA) with single-ended input and differential output for multi-standard wireless receivers up to 6 GHz is presented. To relax external RF filters and LNA linearity requirements, an on-chip LC bandpass load is included with a continuously tunable center frequency from 4.6 GHz to 5.8 GHz. The LNA is implemented in 65nm CMOS technology and achieves a measured gain up to 30 dB and an IIP3 linearity between -6.5 dbm and -10.3 dBm. Due to noise cancelation techniques the noise figure (NF) reaches a low value of 1.6 dB in the band of interest. The power consumption is below 16mW at 1.2V single supply. The active chip area is 154μm * 197μm. Therefore the proposed LNA structure is a cost-effective alternative to source-degeneration based narrowband LNA’s with comparable performance. Since wide-band input impedance matching is employed, the LNA can be used in reconfigurable multi-standard wireless applications.

J. Sturm, X. Xinbo, H. Pretl:
"A 65nm CMOS Wide-band LNA with ContinuouslyTunable Gain from 0dB to 24dB",
IEEE International Symposium on Circuits and Systems – ISCAS, pp. 733-736, 2013

A bi-directional active resistor structure with quasifloating gate MOS transistors and non-linearity compensation is used in a resistive negative feedback wide-band LNA implementation enabling a continuously tunable gain from 0dB to 24dB. The LNA has been realized in 65nm CMOS with a minimum noise figure of 2.5dB and IIP3 of -8dBm at highest gain. The LNA bandwidth is from 100MHz to 2GHz, with a power consumption of 12mW and an active area of 0.0375mm2

 

G. Batistell, J. Sturm:
"Filter-less Color Sensor in Standard CMOS Technology",
Proc. 43th European Solid-State Device Research Conference, pp. 123-126, 2013.

An integrated color detector is presented, which is implemented in a standard 130nm CMOS technology without process modification or additional optical components like color filters. The proposed structure consists of vertically and laterally arranged photodiodes, providing color separation based on lateral carrier diffusion and wavelength-dependent absorption depth. Three independent detector output signals with optimized spectral responsivities allows a discrimination between red, green and blue light spectral components. Linear transformation can be used to realize standardized colorimetric R,G,B or X,Y,Z color space responses. The color detector is therefore a low cost alternative solution for various color sensing applications.

 

G. Batistell, J. Sturm:
"Simulation and Implementation of a Filter-less CMOS Color Detector",
Proc. 49th Conference on Microelctronics, Devices and Materials (MIDEM), pp. 167-172, 2013.

An standard CMOS color detector is presented based on vertically and laterally arranged photodiodes, providing color separation based on lateral carrier diusion and wavelength-dependent absorption-depth. The optical and electrical simulations are performed and the interferences caused by the Oxide/Nitride stack are analyzed. The proposed structure is implemented in a standard 130nm CMOS technology. Three independent detector output signals with optimized spectral responsivities allow a discrimination between red, green and blue light spectral components. In the presented solution color separation can be achieved without modifications of the CMOS process or color filters. The color detector is therefore a low cost alternative solution for various color sensing applications

 

G. Batistell, J. Sturm:
"Standard CMOS Color Sensor based on laterally and vertically arranged photodiodes",
Proc. Austrochip Conference, pp. ????, 2013.

An integrated color detector is presented as an alternative solution for low cost color sensing applications. The detector consists of vertically and laterally arranged photodiodes providing color separation based on lateral carrier diffusion and wavelength-dependent absorption depth. The proposed detector is implemented in a standard 130nm CMOS technology without process modification or color filters. The proposed solution provides three independent output signals with spectral responsivities optimized to short, middle and long wavelengths. The R,G,B or X,Y,Z standard color representation can be realized by a linear transformation of the output signals.

X. Xiang, J. Sturm:
"Tunable Linear MOS Resistor for RF Applications",
Silicon Monolithic Integrated Circuits in RF Systems, 2012.

This paper discusses a continuously tunable linear MOS resistor with bi-directional characteristics. The proposal is based on a 2nd order non-linearity cancellation and is implemented by quasi-floating-gate (QFG) technique. The resistor is optimized for speed, noise and linearity, which makes it well-suited for tunable RF amplifiers. Parallel slices were introduced to enlarge the tuning range. A switching strategy is implemented to guarantee monotonic tuning with limited linearity loss. A testchip is fabricated in 65nm CMOS technology, which shows a -40dB distortion with moderate overdrive voltage and 200mV peak to peak signal amplitude and a high tuning ratio of 19. This MOS resistor has no static power consumption and a layout area of 39um x37um.

 

X. Xiang, J. Sturm:
"Performance Study of a 65nm CMOS Tuneable Gain LNA",
in Proceedings of Austrochip 2012, pp. 47-50, 2012.

This paper is based on a 65nm CMOS tunable active resistor structure (ACR) and investigates the performance of a continuously tunable gain low-noise amplifier (LNA) implementation. The study of proposed ACR structure used in an existing LNA architecture shows a gain tuning range of 27dB with almost no noise figure degradation compared to a switchable poly resistor array. The input referred 1dB compression point and the 3-order intercept point IIP3 is even superior. A higher bandwidth and no static power consumption makes the ACR well suitable for a resistive feedback LNA to realize a continuously tunable gain in a multistandard SOC wireless receiver.

 

Xiao Wang, Johannes Sturm, Na Yan, Xi Tan, and Hao Min:
"0.6–3-GHz Wideband Receiver RF Front-End With a Feedforward Noise and Distortion Cancellation Resistive-Feedback LNA",
IEEE Trans. Microw. Theory Techn., Vol. 60, No. 2 , pp. 387-392, 2012.

A novel wideband receiver RF front-end, including a resistive negative feedback wideband low-noise amplifier (LNA) with feedforward noise and distortion cancellation and a current commutating down conversion passive mixer with biquad trans-impedance amplifier, is presented in this paper. In comparison to conventional resistive negative feedback LNAs, theory analysis and experimental results for the proposed LNA circuit shows improved performance parameters, including voltage gain, noise figure (NF), and input-referred third-order intercept point (IIP3), especially helpful for wideband LNA design in modern deep-submicrometer CMOS. A wideband receiver RF front-end fabricated in 0.13-um CMOS, based on the proposed feedforward noise and distortion-cancellation resistive-feedback LNA, has 42–48-dB conversion gain with 0.8–12-MHz tunable IF 3-dB bandwidth and 12-dB adjacent channel selectivity at 2 , 14-dBm IIP3, and 3-dB NF double-sideband with 10-kHz flicker-noise corner frequency.

 

Chi Zhang, Erwin Ofner:
"Design Considerations for an Integrated Parametric Equalizer for Audio Applications",
in Proceedings of Austrochip 2012, Oct. 2012, Graz, pp51-54, ISBN 978-3-9501635-3-7.

Design considerations for the integration of a five-band parametric audio equalizer are described in this paper. Five 2nd order sections (biquads) are cascaded to amplify or attenuate five different frequency bands in order to adjust the sound to microphones, speakers or room acoustics. Each section can be configured in terms of gain, center frequency and bandwidth. In a first step a Matlab program determines the effect of limited coefficient wordlength on frequency and gain error of individual sections as well as the complete equalizer. For the on-chip computation of the biquad coefficients from specification parameters a CORDIC processor is proposed. Different biquad structures are compared next for performance (area, power, quantization noise). Finally a cascade of five sections is compared to a five-time multiplexed implementation and the proposed equalizer module including interface circuits described.

Matvey Geldin, Andrea Fant, Johannes Sturm:
“Second Order Effects in Multislope A/D Converters”,
in Proceedings of Austrochip 2011, Sept. 2011, Vienna, pp11-15, ISBN 978-3-200-02384-0. 

The purpose of this paper is to show the influence of several second-order effects on the resolution of a multislope ADC. A current mode, multislope ADC is proposed to be used as innovative alternative in an Ambient Light Sensor (ALS). This paper introduces important second order effects in a multislope ADC, checks their contribution and influence in a recent CMOS technology and offers possible solutions for them. The results will be revealed and discussed.

 

Shravan Kumar Kada, David Astrom, Johannes Sturm:
“Temperature and Process Compensated Oscillator in 0.13μm CMOS IC Technology”
in Proceedings of Austrochip 2011, Sept. 2011, Vienna, pp21-25, ISBN 978-3-200-02384-0.

This paper presents the design of a temperature and process compensated oscillator in a 0.13μm CMOS technology process. The oscillator utilizes a bias technique to compensate for temperature and process variations of output frequency. The obtained frequency is based on a 5-stage differential ring oscillator and a compensating circuit. The compensating circuit uses simultaneous compensation of both temperature and process variations. Simulations with temperature variations from -400C to 1500C and process corners variations show an overall frequency accuracy of ±7.8% with a center frequency of 51MHz. The oscillator is intended to serve as a reference clock for PLL. No external components are needed in the proposed oscillator.

Xiao Wang, Wolfgang Aichholzer, Johannes Sturm:
"A 0.1 - 4GHz Resistive Feedback LNA with Feedforward Noise and Distortion Cancelation",
36th European Solid-State Circuits Conference, September 2010, Sevilla, pp406-409, ISBN 978-I-4244-6660-3.

A novel resistive negative feedback wideband lownoise amplifier (LNA) with feedforward noise and distortion cancelation is presented in this paper. In comparison to conventional resistive negative feedback LNA's the proposed LNA circuit shows improved performance parameters including voltage gain, noise figure (NF) and input-referred third-order
intercept point (IIP3). Especially for wideband LNA design's in deep sub-micrometer CMOS technologies, the proposed noise cancelation is efficient. A testchip is fabricated in 65nm CMOS. Measurement results show an LNA performance of 24dB voltage gain, 2dB NF, -5.5dBm IIP3 and S11<-10dB over 0.1-4GHz frequency range. The circuit consumes 12mW and the core layout size is 50μm×80μm.

 

S.Dali, X.Wang, W. Aichholzer, J. Sturm:
"Wideband LNAs with Noise and Distortion Cancelation",
in Proceedings of Austrochip 2010, Oct. 2010, Villach, pp27-31, ISBN 978-3-200-01945-4.

This paper presents two broadband low noise amplifiers (LNAs) suitable for multistandard wireless receivers. The LNAs have been implemented in 65nm CMOS technology. To provide low noise input impedance matching, a negative-shunt feedback amplifier has been proposed. Moreover, a feedforward noise cancelation technique has been used to ensure low noise figure. The first version LNA1 is a variable gain LNA while the second version LNA2 is an improved version but with constant gain. LNA1 achieves a simulated noise figure less than 1.94dBm at the highest gain (25dB) over a wideband frequency (0.1-2)GHz. The gain of LNA1 is variable over a wide range (14dB-25dB) and S11 is less than -19dB over the entire desired frequency band. IIP3 is -6.5dBm at the highest gain. A testchip of LNA2 has been fabricated in 65nm CMOS. Measurement results show an enhanced LNA performance of 24dB voltage gain, 2dB NF, -5.5dBm IIP3 and S11<-10dB over (0.1-4)GHz frequency range. The circuit consumes 12mW and the core layout size is 150μmx80μm.

 

Xinbo Xiang, Johannes Sturm:
"CMOS Active Resistor for RF Applications",
in Proceedings of Austrochip 2010, Oct. 2010, Villach, pp37-41, ISBN 978-3-200-01945-4.

The implementation of active MOS resistors (ACR) is well-established for high resistor values in analog integrated circuits mainly for low-speed applications. This paper presents a variable, linear, active MOS resistor for high-speed RF applications, based on 65nm CMOS technology. Challenging RF performance parameters like noise figure and linearity will be analyzed in comparison to standard poly resistors. The simulation of proposed ACR structure shows noise degradation at 1GHz of only 5~6% compared to a poly resistor and a 1dB compression point of +0.2dBm. In a low noise amplifier application example, the noise figure degrades by only 0.06dB compared to a passive resistor. The input referred 1dB compression is -13.6dBm and the 3-order intercept point IIP3 is +2.9dBm, with 0.11mW power consumption which makes the ACR suitable for modern integrated CMOS RF-frontends.

 

Yingwei Wang, Chi Zhang, Erwin Ofner, Lucas Groposo:
"Third Order Delta Sigma Modulator for Portable Audio",
in Proceedings of Austrochip 2010, Oct. 2010, Villach, pp79-82, ISBN 978-3-200-01945-4.

A third-order Delta Sigma Modulator (DSM) for a Digital to Analog Converter (DAC) used in portable audio applications is designed and analyzed in this paper. To reach the high SNR and low-power consumption requirements, a multi-bit output scheme and dynamic dithering are used. Data-weighted averaging is applied to solve the mismatch error which is introduced by the multi-bit output. Due to the natural low pass character of the Signal Transfer Function (STF), a cascade of resonators with distributed feedback (CRFB) topology can simplify the interpolation filter. With this structure, >110dB SNR and <0.1dB pass band ripple over a bandwidth of 20kHz are achieved.

 

Graciele Batistell, Johannes Sturm:
"Lateral Junction Color Detector in Standard CMOS Technology",
in Proceedings of Austrochip 2010, Oct. 2010, Villach, pp109-113, ISBN 978-3-200-01945-4.

The investigation of an integrated color detector is presented in this paper. The proposed structure consists of integrated photodiodes designed in standard CMOS technology without process modification and expensive color filters. Instead of using a vertical photodiodes stack as the classical approach for color separation, the photodiodes on the proposed structure are laterally arranged along the surface, providing color separation based on lateral carrier diffusion. The color detector is proposed as low cost alternative solution for color sensing applications. 2.5D device simulations of the responsivity behavior, the influence of detector geometry and doping concentrations is analyzed.

Erwin Ofner, Chi Zhang, Haifeng Zhou:
"Integration of Low-Power Decimation Filters",
3. Forschungsforum der österreichischen Fachhochschulen, April 2009, Villach, pp147-151, ISBN 978-3-853912850.

The need for extended operation and standby times in modern battery powered electronic equipment requires advanced low power design methods. This paper describes research activities in two projects, both targeted at low power integration of digital functions frequently used in components for popular consumer applications. While work in a project which has already been completed, delivered low power digital modules for 3rd generation mobile phones, quite similar low power components have been developed for portable digital audio circuits like MP3 players – often integrated into mobile phones as well. Two design examples are given: the design of a multi-mode decimation filter for the Analog to Digital Converter (ADC) of a GSM/UMTS mobile terminal and the design of a test vehicle for an ultra low power decimation filter for the ADC in portable digital audio equipment. In both cases new low power filter architectures and circuits were designed, fabricated on testchips and evaluated to reach attractive results.

 

Wolfgang Aichholzer, Johannes Sturm:
"A 65nm CMOS RF Power Detector with Integrated Offset Storage",
in Proceedings of Austrochip 2009, Oct. 2009, Graz, pp5-8, ISBN 978-3-9501635-1-3.

In this work we present a fully differential and symmetric power detector (PD) used for mobile applications. The information of the signal power is used in an automatic gain control circuit (AGC) to maintain the low-noise RF amplifier’s (LNA) gain to avoid saturation problems. The proposed PD structure uses a fully differential rectifier structure based on "self-mixing" technique. The circuit uses an offset storage method to improve the offset voltage and is implemented in 65nm CMOS technology.

 

Oleksandr Melnychenko, Sergii Zaiets, Manfred Ley:
"Low-Power High-Speed Decimation Filter in 65 nm CMOS",
in Proceedings of Austrochip 2009, Oct. 2009, Graz, pp75-79, ISBN 978-3-9501635-1-3.

The design and implementation of a high-speed low power decimation filter using a deep-sub-micron digital standard cell library is presented. The choice of a polyphase non-recursive decimation filter is explained and some flexibility of the polyphase decimation filter implementation is demonstrated. The description starts from system level and goes via synthesis and layout to the backannotated circuit simulation. Some problems of synthesis and routing influencing the design are discussed. Finally results after layout and their analysis are presented, which demonstrate the correct work of the designed decimation filter at the specified clock speed of 2.56 GHz with a power consumption of 1.2 mW.

Haifeng Zhou, Chi Zhang, Erwin Ofner:
"Low-Power Decimation Filter for Portable Audio Applications",
in Proceedings of Austrochip 2008 in Linz, Oct 2008, pp48-51, ISBN 987-3-200-01330-8.

This paper describes a low-power decimation processor module for a sigma-delta ADC used in portable audio applications. Multi-rate decimation filters use running sum filters as 1st stage, which, despite their simple architecture, contributes most to the filter’s power consumption due to the highest sample rate. Non-recursive implementations can reduce the power to less than 30% compared to the traditional CIC architecture. Further savings can be achieved by moving the running sum filter into the analogue domain and using transistor level design and power optimization techniques. A 3rd order running sum filter with a decimation factor M=4 for a 4 bit input was designed and fabricated on a test-chip using a standard 0.35um CMOS 2P3M fabrication technology. Measurements show a power consumption of 3.75uW for the filter operated at 1.2V and 3.072MHz.

 

Stephen T. Burgess, Erwin Ofner:
"Recursive All-Pass Interpolation Filters for Digital Audio Applications",
in Proceedings of Austrochip 2008 in Linz, Oct 2008, pp52-55, ISBN 987-3-200-01330-8.

This paper investigates the use of recursive all-pass structures as a potential means to create more efficient multistage interpolation filters for audio applications. Quasilinear and nonlinear versions are compared with a conventional FIR reference design in terms of power consumption, area, and linearity. Analysis results take into account circuit switching activity and parasitics extracted from a 0.35um standard cell layout. It is demonstrated that a nonlinear all-pass filter can reduce first stage area and power by more than 50% and can further be used to form an optional all-pass/FIR hybrid filter solution.

 

J. Sturm, H. Zimmermann,
"Photodiode Modeling for Optoelectronic Integrated Circuits",
Semiconductor Conference Dresden, Proceedings of SCD (2008).

This paper reports on the development of a novel photodiode SPICE simulation model for optoelectronic integrated circuits (OEIC) applications. The proposed model includes most significant high-speed properties like carrier drift and diffusion effects for arbitrary input light waveforms but also wavelength and voltage dependent photodiode sensitivity as well as surface light reflection. The model for a double photodiode structure integrated in a standard 0.5um BiCMOS IC technology is realized as a simple electrical circuit using SPICE primitives only. It can be used for time dependent transient simulations and also for frequency dependent AC simulations with a very high simulation speed.

Chi ZHANG, Erwin OFNER:
"ASIC Implementation of Low Power Decimation Filter for UMTS and GSM Sigma-Delta A/D Converter ",
in Proceedings of IWSDA'07 in Chengdu, Sep 2007, pp224-228, ISBN 1-4244-1074-6.

This work proposes an ASIC implementation of low power non-recursive decimation filters in a GSM and UMTS dual mode sigma delta ADC. An alternative that saves 70% to 80% power consumption to the standard CIC approach is discussed here with a decimation factor of m-th power of two and m-th power of three. More research is done to find the break-even point between power consumption and silicon area for non-recursive and recursive architectures. The chip is fabricated in 0.35µm CMOS and consumes 4.72mW in GSM and 5.54mW in UMTS mode, both at Vdd=2.5V.

 

Manfred Ley, Gerald Klatzer, Mario Nussbaumer:
"USB Audio Streaming System with FPGA, an Example of Project-Based Education in Microelectronics",
Presentation on 30th International Convention MIPRO07, Opatija, Croatia, Proceedings Microelectronics, Electronics and Electronic Technologies p170-174, ISBN 978-953-233-032-8

This paper gives an overview of project-based education based on microelectronics system-on-chip design carried out at the University of Applied Science in Villach, Austria. During a one-year students' project an audio streaming system was developed, which allows the real time replay of audio data from a PC via USB port to a speaker directly connected to FPGA hardware. The whole system consists of PC control software, a windows realtime kernel driver, FPGA hardware for implementation of the USB controller, control logic, data rate converter and all signal processing for a one-bit delta-sigma digital to analog converter. In addition to a description of the complex real time software - hardware system developed, the focus of this paper is on didactical and organisational aspects of arranging lectures in informatics, microelectronics, realtime systems, digital signal processing and DtoA-converters around a given project task. Finally, the students involved describe their experience over two semesters of very intensive project-based learning.

 

Chi ZHANG, Erwin OFNER:
"A 2.5V, 5mW UMTS and GSM Dual Mode Decimation Filter for Sigma Delta ADC",
in Proceedings of A-SSCC 2007 in Jeju, Nov 2007, pp272-275, ISBN 1-4244-1359-1.

This paper describes a decimation processor for a dual-mode sigma-delta ADC for GSM and UMTS mobile standards. Partly contradictory requirements like high dynamic range and low bandwidth for GSM and vice versa for UMTS need decimation factors of M=144 (GSM) and M=8 (UMTS). A multi-rate filter architecture, which allows best hardware re-use for both mobile standards, is selected. Since the ADC is to be integrated into the power management component of the mobile terminal utilizing a 0.35µm CMOS technology, special attention has been given to silicon area and power consumption of the component, while maintaining a standard design flow for the implementation. The processor covers 1.13 mm2 of silicon and consumes 4.72mW in GSM and 5.54mW in UMTS mode, both at Vdd=2.5V.

 

Chi Zhang, Erwin Ofner
"Low Power Non-Recursive Decimation Filters",
in Proceedings of ICECS 2007 in Marrakech, Dec 2007, pp804-807, ISBN 1-4244-1378-8

This work proposes low power non-recursive decimation filters in a GSM (Global System for Mobile communication) and UMTS (Universal Mobile Telecommunications System) dual mode sigma delta ADC. The proposed technique is an alternative to the standard CIC (Cascaded Integrator-Comb) approach with a decimation factor of m-th power of two and m-th power of three. 70% to 80% power consumption can be saved by the non-recursive structure compared to the Hogenauer CIC architecture. More research is done to find the break-even point of silicon area for non-recursive and recursive architectures. A low power decimation filter chip for a UMTS and GSM dual mode sigma delta A/D converter is fabricated in 0.35um CMOS (Complementary Metal-Oxide- Semiconductor) and consumes 4.72mW in GSM and 5.54mW in UMTS mode, both at Vdd=2.5V.

Simon Hainz, Erwin Ofner, Dirk Hammerschmidt, Tobias Werth, Herbert Grünbacher:
"Position Detection in Automotive Application by Adaptive Inter Symbol Interference Removal",
in Proc. IEEE Sensors 2006, Daegu, Korea.

Incremental magnetic field sensors are frequently used in automotive applications for crankshaft and camshaft position measurements. Highest possible phase accuracy and disturbance immunity (air gap and temperature variations, noise) are the primary performance requirements for such sensor systems. An analog measurement signal is generated from a magnetic field sensor and the position information is obtained using state of the art peak or zero crossing detection in the analog or digital domain. While phase jitter of peak or zero crossings can be minimized, these techniques cannot take into account variations of peak and zero crossing positions due to air gap variations. A Decision Feedback Equalizer (DFE) was adapted to remove this systematic error. For this purpose a physical model of the measurement environment (magnetic field) was derived and verified by Finite Element simulations (FEM). With simplifications the model delivered an analytical function for magnetic field calculations, which serve the adaptive algorithm for the DFE.

 

Simon Hainz, Dirk Hammerschmidt, Erwin Ofner, Tobias Werth:
"Improving Phase Accuracy by Removing Systematic Phase Error Introduced by Inter Symbol Interference",
'in Proc. Eurosensor 2006, Göteborg, Sweden.

Magnetic field sensor-systems in automotive applications follow various switching concepts to obtain the speed and angle information. Since these concepts do not care about the systematic phase error introduced by air gap variations, a new Decision Feedback Equaliser (DFE) system was developed. The presented system can remove the systematic phase error and generate a sensor output without dependence on air gap variations.

 

Chi ZHANG, Erwin OFNER:
"A 36 Decimation Factor Low Power CIC Filter Application",
in Proc. Austrochip 2006, Vienna, Austria.

A thirty-six decimation factor CIC filter application is proposed based on low power non-recursive structures. The proposed technique is an alternative to the standard CIC approach with a decimation factor of m-th power of two and m-th power of three. More research is done to find the break-even point of silicon area for non-recursive and recursive architecture of decimation filters with filter order 4. Around 70% of power can be saved by the non-recursive structure compared to the Hogenauer CIC architecture.

 

Chi ZHANG, Erwin OFNER:
"Low Power Decimation Filter Design for GSM Sigma Delta ADC Application",
in Proc. 8th International Conference on Solid-State and Integrated-Circuit Technology, Shanghai, China.

A low power decimation filter design for GSM Sigma-Delta A/D converter application is proposed in this paper. The main power consumption CIC part is based on non-recursive structure that is an alternative to the standard CIC approach with a decimation factor of m-th power of two and m-th power of three. More research is done to find the break-even point of silicon area for non-recursive and recursive architecture of decimation filters with filter order 4. More than 70% of power can be saved for a filter with decimation factor 36 and filter order 4 by the non-recursive structure compared to the Hogenauer CIC architecture.

J. Nurmi, J. Madsen, E. Ofner, J. Isoaho, H. Tenhunen,
"The SoC-Mobinet Model in System-on-Chip Education",
in Proc. MSE05, June 2005, Anaheim, USA.

This paper describes the model of developing SoC curricula jointly by industry and academia, where joint effort research results are turned into course contents for SoC-curricula and industry training activities.

S. Hainz, E.Ofner, D. Hammerschmidt, D. Tatschl and T. Werth:
"Data Predictive Decisoin Feedback Equalizer for Position Detection in Automotive applications",
in Proc. ICIT 2004, Hammamet, Tunisia

In automotive application magnetic field sensors are commonly applied for position detection of rotating objects (wind shield wiper, speed, engine applications). Especially engine applications require high accuracy. The main demands for such sensors are correct phase and disturbance (air gap, temperature, noise) immunity. Nowadays sensor-systems follow various hysteresis concepts to avoid jitter. These circuits are robust against noise; however, do not remove jitter introduced by Inter Symbol Interference (ISI). To overcome this problem, a Decision Feedback Equalizer (DFE) was adapted. Based on the standard DFE, a new filter structure is proposed and called data predictive DFE (pDFE). The main advantages of the pDFE are the enhancements in phase detection and the lack of latency in the signal path. This paper explains the new pDFE structure and demonstrates the operation mode with simulations.

 

E. Ofner, J. Nurmi, J. Madsen, J. Isoaho and H. Tehunnen:
"SoC-Mobinet, R&D and Education in Systems-on-Chip Design",
in Proc. SoC 2004, Tampere, Finnland

With fabrication technologies enabling the integration of a billion transistors and allowing giga-hertz frequencies, complex systems (System-on-Chip, SoC) can be realized on a single die. The design of such systems provides tremendous challenges to industry and academia. Universities need to invest a huge effort to restructure their related engineering curricula, which is only possible in close co-operations with industry and other Universities. This paper describes a project, co-funded by the European Commission and by industry, where in a joint effort related research results are turned into course contents for SoC-curricula and industry training activities.

 

M. Castelli and E. Ofner:
"100 MHz Floating Point Processing Unit - A Feasibility Study",
in Proc. DCIS 2004, Bordeaux

This paper discusses several architectures for a floating-point processing module capable to execute 100 million multiply-and-accumulate (MAC) instructions per second. The module will be used stand-alone or as add-on to a software programmable DSP core, using a 0.35µm CMOS technology for mixed-signal integrated circuits operating at 3.3V. Pipelining and parallel operation will be considered in order to meet the specified goals.

 

M. Castelli, A. Hradetzky, M. Ley and E. Ofner:
"High-Level Hardware Synthesis of Multi-Rate Filters",
in Proc. Austrochip 2004, Vienna

Multi-rate decimation and interpolation filters are required for over-sampled data converters, which are frequently used in System-on-Chip solutions. Configurable IP modules exist for this purpose, however, compromises in silicon utilization and excessive power consumption are often the price paid for flexibility. An optimization of these multi-rate filter parameters is time consuming, unless a suitable design methodology is available. This paper describes a script based high-level hardware synthesis approach for multi-rate filters to overcome this problem.

 

S. Hainz, E.Ofner, D. Hammerschmidt, D. Tatschl and T. Werth:
"Position Detection by Inter Symbol Interference Removal for Engine Applications",
in Proc. Austrochip 2004, Vienna

Magnetic field sensors are commonly used for position detection of rotating objects in automotive applications (wind shield wiper, speed, engine applications). Especially position detection in engine applications (crankshaft and camshaft) requires high accuracy and sensor requirements regarding correct phase and disturbance immunity (air gap, temperature, noise) are challenging. Nowadays sensorsystems follow various hysteresis concepts to avoid jitter. These circuits are robust against noise; however, they don’t remove jitter introduced by Inter Symbol Interference (ISI).

 

E. Ofner and A. Blaickner:
"SoC-Mobinet, R&D and Education in Systems-on-Chip Design",
in Proc. Austrochip 2004, Vienna

With fabrication technologies enabling the integration of a billion transistors and allowing gigahertz frequencies, complex systems (System-on-Chip, SoC) can be realized on a single die. The design of such systems provides tremendous challenges to industry and academia. Universities need to invest a huge effort to restructure their related engineering curricula, which is only possible in close collaborations with industry and other universities. This paper describes a project, co-funded by the European Commission and by industry, where in a joint effort related research results are turned into course contents for SoC-curricula and industry training activities. Carinthia Tech Institute, School of Electronics (CTI), is a partner in this consortium and contributes with R&D and development of new course modules.

 

A. DeVora, M. Ley, E. Ofner, H. Grünbacher,
"A High Speed Radix-4 Hardware Divider for ASIC's",
in Proc. Norchip, November 2002, Copenhagen, Denmark

Configurable DSP cores optimized for high-level programming, as required for System on Chip (SoC) design, need architectures, which generate critical design constraints and require a high degree of flexibility for all building blocks. High performance arithmetic modules are the key elements of all software programmable processors cores. In addition, for special requirements in terms of functionality, speed, power consumption or cost, hard-wired implementations often become necessary. While the design of fast and efficient adders or multipliers is well covered in literature and well supported by IP providers, the design of a flexible, high performance divider module remains a challenge. This paper describes the design of a configurable Radix-4 Hardware Divider, carried out within the scope of project SoC-Mobinet.

A. DeVora, M. Ley, E. Ofner, H. Grünbacher,
"A High Speed Radix-4 Hardware Divider for ASIC's",
in Proc. Norchip, November 2002, Copenhagen, Denmark.

Configurable DSP cores optimized for high-level programming, as required for System on Chip (SoC) design, need architectures, which generate critical design constraints and require a high degree of flexibility for all building blocks. High performance arithmetic modules are the key elements of all software programmable processors cores. In addition, for special requirements in terms of functionality, speed, power consumption or cost, hard-wired implementations often become necessary. While the design of fast and efficient adders or multipliers is well covered in literature and well supported by IP providers, the design of a flexible, high performance divider module remains a challenge. This paper describes the design of a configurable Radix-4 Hardware Divider, carried out within the scope of project SoC-Mobinet.

 

Manfred Ley; Christian Madritsch
“Distributed Embedded Safety Critical Real-Time Systems, Design and Verification Aspects on the Example of the Time Triggered Architecture”,
Invited paper 39th International Conference on Microelectronics, Devices and Materials MIDEM03, 1.10 - 3.10.2003, Ptuj, Slovenia, Proceedings p51-62, ISBN 961-91023-1-2

The Time Triggered Architecture (TTA) and its related communication protocol, TTP/C is an emerging communication principle for distributed fault-tolerant real-time systems. Typical applications are safety-critical digital control systems such as drive-by-wire and fly-by-wire. This paper highlights the hardware / software architecture and design of the first industrial single chip communication controller for the Time Triggered Protocol (TTP/C). An application specific RISC core with several specialized peripheral blocks, RAMs, flash memory and analog cells was implemented together with necessary protocol firmware to fullfill both cost and safety requirements. Whereas the controller chip itself can be seen as an embedded system, the composability characteristic of TTA enables a hierarchical system design style with nodes and communication clusters as higher level system components embedded into an application device like a car or airplane. A complete framework for hardware / software co-simulation and verification across all levels of hierarchy was buildt up to support the design work from chip to system level. Furthermore, system reliability and fault behaviour of a safety critical system has to be shown to safety certification authorities. Extensive fault injection experiments have been performed at simulation level and physical level to proove the concept, fault model and resulting implementation of an embedded TTA control system.

E. Ofner, A. Pester, H. Grünbacher,
"A Matlab Toolbox for VLSI-Design of Bit-serial FIR Filters as Example of Problem Based Learning in Microelectronics Education",
in Proc. of 4th European Workshop on Microelectronics Education EWME 2002, May 2002, Baiona, Spain.

Problem based learning is a frequently used approach in engineering education and was successfully introduced at Carinthia Tech Institute two years ago. Special knowledge in focus areas is provided to students in the form of two-semester student projects, which are accompanied by suitable courses and special assistance in project management. Selected project topics must be both suitable for education and need to have industrial relevance. In the microelectronics area the development of Matlab scripts for the optimization and VLSI implementation of bit-serial FIR filters is an ideal topic for a student project. The work contributes to hard-wired implementations of digital signal processing functions, which are of paramount importance to mixed-signal VLSI and System-on-Chip (SoC) design. Reaching highest sampling frequencies, consuming lowest power and reducing hardware cost to an absolute minimum are typical requirements and leave plenty of room for creative work.

 

J. Nurmi, J. Isoaho, H. Tenhunen, J. Madsen, E. Ofner, I. Ring Nielsen,
"SoC-Mobinet - A Project for Collaborative System-on-Chip Curricula Development with Industrial Support",
in Proc. of 4th European Workshop on Microelectronics Education EWME 2002, May 2002, Baiona, Spain.

The paradigm shift taking place when moving to System-on-Chip design requires huge efforts from the universities to restructure the related engineering curricula. Networking and cooperation is needed for success, also between the universities and industry since the industry possesses the best knowledge of the practical needs in complex system implementation. In this paper, a unique effort to survive the paradigm shift is described. In an EU-project, competence is built into the universities by MSc and PhD thesis research cofunded by the industry. The competence is turned into curriculum and course contents in a distributed centre of excellence, and returned to the industry in the form of training activities.

 

A. Pester, E. Ofner, H. Grünbacher, A. Moore,
"Problem Based Learning in Microelectronics: Approach, Experience, Examples",
in Proc. "Entwicklung einer technischen Elite" at the University Kharkiv, May 2002, Kharkiv, Ukraine.

Problem based learning (PBL) as a total approach to learning has been widely applied in various disciplines, including engineering and was successfully introduced at Carinthia Tech Institute (CTI) School of Electronics three years ago. Two-semester projects focusing on core areas of electronics and accompanied by both electronic courses and assistance in project management are offered to students. Project topics, selected by students, must be practical, meet electronic curriculum objectives, and have industrial relevance. In addition to the technical skills learned in the process of completing the project, students learn how to work in a team, develop self-directed learning strategies, manage time and resources, and present the results of their work in oral and written form.

 

M. Ley, H. Grünbacher,
“VLSI COMMUNICATION INTERFACE FOR TIME-TRIGGERED REAL-TIME SYSTEMS”,
e&i Elektrotechnik und Informationstechnik 7/8-2002.

This paper describes the design of a VLSI communication controller for the Time Triggered Protocol (TTP/C) as the result of a microelectronics development project done at Fachhochschule Technikum Kärnten in cooperation with industrial partners. TTP/C is an emerging communication protocol for fault-tolerant real time systems. Typical applications are safety-critical digital control systems such as brake-by-wire, steer-by-wire and fly-by-wire. We applied a VHDL based design flow to implement digital standard cell logic, RAMs, flash memory and analog cells into a 27 mm² chip using a 0.35µ CMOS technology. First fully tested production samples are available and proved the design to be first time right. At this year's SAE (Society of Automotive Engineers) world congress in Detroit, out of more than 5000 innovations presented, the TTP controller IC was nominated as 'Top Product of the Year'. Keywords: Time Triggered Protocol, TTP/C, single-chip controller

 

M. Ley, H. Grünbacher,
“TTA-C2 a SINGLE CHIP COMMUNICATION CONTROLLER for the TIME-TRIGGERED-PROTOCOL”.
Proceedings ICCD, International Conference on Computer Design 2002, Freiburg, Germany.

This paper describes the architecture and implementation of the first industrial single chip communication controller for the Time Triggered Protocol (TTP/C). TTP/C is an emerging communication protocol for fault-tolerant real time systems. Typical applications are safety-critical digital control systems such as drive-by-wire and fly-by-wire. We applied a VHDL based design flow to implement an application specific RISC core with several specialized peripheral blocks, RAMs, flash memory and analog cells. For production of the 27 mm² chip a 0.35µ Flash-CMOS technology is used. Fully tested samples are already available and proved the design to be “first time right”.

 

A. Hradetzky, M. Castelli, E. Ofner, H. Grünbacher,
"Matlab Toolbox Functions for Design and Implementation of Bit-serial Poly-phase FIR Filters",
in Proc. Austrochip 2002, October 2002, Graz, Austria, pp. 141-147.

System-on Chip (SoC) design techniques require high performance, highly re-usable and configurable building blocks. Mixed-signal SoCs frequently have over-sampled data converters on board which need multi-rate decimation and interpolation filters. Hard-wired VLSI implementations of these filters are used to reach highest sampling frequencies, to consume lowest possible power and to reduce the hardware cost to a minimum. A Matlab toolbox serving as design platform for the implementation of bit-serial FIR filters was enhanced with functions for poly-phase FIR filters as used in multistage decimation and interpolation modules.

 

A. DeVora, M. Ley, E. Ofner, H. Grünbacher,
"A High Speed Radix-4 Hardware Divider for ASIC's",
in Proc. Norchip, November 2002, Copenhagen, Denmark.

Configurable DSP cores optimized for high-level programming, as required for System on Chip (SoC) design, need architectures, which generate critical design constraints and require a high degree of flexibility for all building blocks. High performance arithmetic modules are the key elements of all software programmable processors cores. In addition, for special requirements in terms of functionality, speed, power consumption or cost, hard-wired implementations often become necessary. While the design of fast and efficient adders or multipliers is well covered in literature and well supported by IP providers, the design of a flexible, high performance divider module remains a challenge. This paper describes the design of a configurable Radix-4 Hardware Divider, carried out within the scope of project SoC-Mobinet.

 

C. Panis, A. Schilke, H. Habiger, J. Nurmi,
"An Automatic Decoder Generator for a scaleable DSP architecture",
in Proc. Norchip, November 2002, Copenhagen, Denmark.

Scaleable and flexible DSP cores are necessary to obtain the area and power dissipation requirements of SOC applications. The drawback of flexible structures is the additional verification and test effort. One approach to overcome this drawback is the usage of generators producing correct code by construction. The paper describes the structure and implementation of a generator, which generates VHDL code for an instruction decoder. The input of the generator is the chosen instruction set description. This enables the definition of application specific instruction sets to reach high code density, low power dissipation and increased performance. The development of the Decoder Generator has been done within the scope of the project SOC-Mobinet (System on Chip for Mobile Internet)

E. Ofner, A. Pester und H. Grünbacher,
"Projektorientierte Ausbildung für zukünftige Mikroelektronik-Entwickler am Studiengang Elektronik der Fachhochschule Technikum Kärnten",
ÖVE Schriftenreihe Nr. 26 Informationstagung Mikroelektronik 2001, Oktober 2001, pp. 277-282.

Am Studiengang Elektronik der FH Technikum Kärnten in Villach wird seit zwei Jahren die fachliche Vertiefung in der Form von projektorientierter Ausbildung durchgeführt. Vertiefte Spezialkenntnisse sollen mit Projekterfahrungen gekoppelt werden. Am Beispiel eines Projektes aus der Mikroelektronik-Entwicklung werden die wichtigsten Erfahrungen dieser Ausbildungsform exemplarisch dargestellt und Schlussfolgerungen gezogen.

 

E. Ofner, M. Castelli, M. Ley, A. Pester and H. Grünbacher,
"Matlab Toolbox for VLSI-Design of Bit-serial FIR Filters",
in Proceedings of Austrochip 2001, October 2001, pp. 85-91.

Hard-wired implementation of digital signal processing functions has been of paramount importance in terms of mixed-signal VLSI and System-on-Chip (SoC) design. Reaching highest sampling frequencies, consuming lowest possible power and reducing the hardware cost to an absolute minimum are requirements for hard-wired VLSI implementations. This paper describes a student project in which Matlab scripts for optimization and VLSI implementation of bit-serial FIR filters were developed.

M. Ley, H. Grünbacher,
“TTA-C2, A SINGLE CHIP COMMUNICATION INTERFACE FOR TIME-TRIGGERED REAL-TIME SYSTEMS”,
Proceedings Austrochip 1999, October 1999, Villach, Austria, pp117-122.

This paper describes the design and implementation of a single chip communication controller for the Time Triggered Protocol (TTP/C). TTP/C is an emerging communication protocol for fault-tolerant real time systems. Typical applications are safety-critical digital control systems such as brake-by-wire, steer-by-wire and fly-by-wire. We applied a VHDL based design flow to implement digital standard cell logic, SRAMs, flash memory and analog cells into a 23 mm² single chip controller. The chip will be produced in a 0.35µ CMOS technology and mounted into a 80pin PQFP.

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