Integrated Systems and Circuits Design

Area of studies
Engineering & IT

Level of qualification
2. Cycle (Master)

Qualification awarded
Master of Science in Engineering (MSc)

Mode of study

Duration of study
4 Semesters

ECTS-Credits awarded
120 ECTS


FH site

Tuition fees
€ 363.36

ÖH contribution
€ 18,70


Selected publications 2010

Xiao Wang, Wolfgang Aichholzer, Johannes Sturm:
"A 0.1 - 4GHz Resistive Feedback LNA with Feedforward Noise and Distortion Cancelation",
36th European Solid-State Circuits Conference, September 2010, Sevilla, pp406-409, ISBN 978-I-4244-6660-3.

A novel resistive negative feedback wideband lownoise amplifier (LNA) with feedforward noise and distortion cancelation is presented in this paper. In comparison to conventional resistive negative feedback LNA's the proposed LNA circuit shows improved performance parameters including voltage gain, noise figure (NF) and input-referred third-order
intercept point (IIP3). Especially for wideband LNA design's in deep sub-micrometer CMOS technologies, the proposed noise cancelation is efficient. A testchip is fabricated in 65nm CMOS. Measurement results show an LNA performance of 24dB voltage gain, 2dB NF, -5.5dBm IIP3 and S11<-10dB over 0.1-4GHz frequency range. The circuit consumes 12mW and the core layout size is 50μm×80μm.


S.Dali, X.Wang, W. Aichholzer, J. Sturm:
"Wideband LNAs with Noise and Distortion Cancelation",
in Proceedings of Austrochip 2010, Oct. 2010, Villach, pp27-31, ISBN 978-3-200-01945-4.

This paper presents two broadband low noise amplifiers (LNAs) suitable for multistandard wireless receivers. The LNAs have been implemented in 65nm CMOS technology. To provide low noise input impedance matching, a negative-shunt feedback amplifier has been proposed. Moreover, a feedforward noise cancelation technique has been used to ensure low noise figure. The first version LNA1 is a variable gain LNA while the second version LNA2 is an improved version but with constant gain. LNA1 achieves a simulated noise figure less than 1.94dBm at the highest gain (25dB) over a wideband frequency (0.1-2)GHz. The gain of LNA1 is variable over a wide range (14dB-25dB) and S11 is less than -19dB over the entire desired frequency band. IIP3 is -6.5dBm at the highest gain. A testchip of LNA2 has been fabricated in 65nm CMOS. Measurement results show an enhanced LNA performance of 24dB voltage gain, 2dB NF, -5.5dBm IIP3 and S11<-10dB over (0.1-4)GHz frequency range. The circuit consumes 12mW and the core layout size is 150μmx80μm.


Xinbo Xiang, Johannes Sturm:
"CMOS Active Resistor for RF Applications",
in Proceedings of Austrochip 2010, Oct. 2010, Villach, pp37-41, ISBN 978-3-200-01945-4.

The implementation of active MOS resistors (ACR) is well-established for high resistor values in analog integrated circuits mainly for low-speed applications. This paper presents a variable, linear, active MOS resistor for high-speed RF applications, based on 65nm CMOS technology. Challenging RF performance parameters like noise figure and linearity will be analyzed in comparison to standard poly resistors. The simulation of proposed ACR structure shows noise degradation at 1GHz of only 5~6% compared to a poly resistor and a 1dB compression point of +0.2dBm. In a low noise amplifier application example, the noise figure degrades by only 0.06dB compared to a passive resistor. The input referred 1dB compression is -13.6dBm and the 3-order intercept point IIP3 is +2.9dBm, with 0.11mW power consumption which makes the ACR suitable for modern integrated CMOS RF-frontends.


Yingwei Wang, Chi Zhang, Erwin Ofner, Lucas Groposo:
"Third Order Delta Sigma Modulator for Portable Audio",
in Proceedings of Austrochip 2010, Oct. 2010, Villach, pp79-82, ISBN 978-3-200-01945-4.

A third-order Delta Sigma Modulator (DSM) for a Digital to Analog Converter (DAC) used in portable audio applications is designed and analyzed in this paper. To reach the high SNR and low-power consumption requirements, a multi-bit output scheme and dynamic dithering are used. Data-weighted averaging is applied to solve the mismatch error which is introduced by the multi-bit output. Due to the natural low pass character of the Signal Transfer Function (STF), a cascade of resonators with distributed feedback (CRFB) topology can simplify the interpolation filter. With this structure, >110dB SNR and <0.1dB pass band ripple over a bandwidth of 20kHz are achieved.


Graciele Batistell, Johannes Sturm:
"Lateral Junction Color Detector in Standard CMOS Technology",
in Proceedings of Austrochip 2010, Oct. 2010, Villach, pp109-113, ISBN 978-3-200-01945-4.

The investigation of an integrated color detector is presented in this paper. The proposed structure consists of integrated photodiodes designed in standard CMOS technology without process modification and expensive color filters. Instead of using a vertical photodiodes stack as the classical approach for color separation, the photodiodes on the proposed structure are laterally arranged along the surface, providing color separation based on lateral carrier diffusion. The color detector is proposed as low cost alternative solution for color sensing applications. 2.5D device simulations of the responsivity behavior, the influence of detector geometry and doping concentrations is analyzed.