System Modeling and Verification – Analog - Lecture Contents

Responsible Lecturer: Eva Tatschl

Chapter 1: Analog Design Flow – Modeling
The challenges in the development process of an analog building block are introduced to the student. Commonly used design strategies are discussed and the Top Down Design Methodology is introduced. The necessary tasks to implement a full Top Down Design and the team structure needed for such an approach are developed

Chapter 2: Matlab
Basic Matlab knowledge is a prerequisite for this chapter. The class discusses Matlab's use as the 4GL commonly applied to do first draft models in Analog Design. The chapter concentrates on the techniques to optimize Matlab code in order to create higher performance models. Also the new tools available to speed up Matlab models are discussed.

Chapter 3: Simulink
Simulink is introduced as a software package for modeling, simulation, and analysis of dynamic systems. Background information on how Simulink works is given. Different solvers, continuous state vs. discrete models, fixed step vs. variable step, hierarchy, subsystems, model testing, verification of a model, assertions are discussed. A Simulink lab exercise is build in class

Chapter 4: Discrete Time Modeling of Analog Blocks
The options for Verifications of SOCs with analog content are discussed and the borders of Analog Simulation shown. The option Discrete Time Modeling is further developed in this Chapter, Co-Simulation in the next chapter. An introduction into VHDL is given and its application for analog models is discussed (Resolved signals, power supply modeling, integration into the design flow – net listing). In class lab-exercises are used to introduce the students to the new concepts.

Chapter 5: Analog Modeling Language VHDL AMS
The limits of VHDL for analog modeling are discussed and VHDL-AMS is introduced. Basic introduction to the language and its concepts (formulation of the differential equations ...) is given. The fundamental differences between quantities and signals is discussed and underlined by in class lab work. The concept of Mixed Signal simulation is introduced and an example executed in class. Discussions about the solvability close this chapter.

Chapter 6: SystemC and SystemC AMS – A Brief Introduction
Channels, Ports, Interfaces, Method and Thread Processes, Synchronization, Simulation Control are discussed. In class examples for SystemC are exercised using the Eclipse programming interface.

 

LAB exercises: 

LAB1
Matlab Model that can calculate DNL and INL for a given Flash ADC

LAB2
Simulink Model of a Flash ADC. Students are assigned a block inside the Flash ADC. The block is to be modeled in Simulink.

LAB3
VHDL Model of a Flash ADC. Every student is assigned a block inside the Flash ADC to be modeled in VHDL.

LAB 4
Modify a Model of an RC-Filter to be a correct VHDL-AMS Model.

 

System Modeling and Verification – Digital - Lecture Contents

Responsible Lecturer: Manfred Ley

System theory
transfer characteristics and behavior, time continuous and discrete systems, mathematical models, system verification, system partitioning and executable specification.

Chip level modeling
system modeling (e.g. SystemC, SystemVerilog), behavioral model, chip level modeling of physical effects, modeling support of HW/SW partitioning, modeling of power consumption.

Structural level modeling (RTL)
timing and synchronization, time continuous and discrete models, analog, digital and mixed-signal structural level models, Power modeling on RTL and gate-level,

Chip level verification
SystemC, MatLab, Power - static and dynamic approaches for power estimation, Early area estimation. 

Structural level verification (RTL, gate level)
Multi-level verification, Modern verification approaches, Regression-based verification - self-testing tests, Formal verification, randomized testbench approaches, directed tests, Power estimation on RTL and gate level

Labs with various CAD tools (Matlab Simulink, ...)