IC-Test Lecture Contents

Chapter 1: Introduction to test
An overview is given to explain the purpose and targets for production test. This chapter describes the types of IC testing, the steps taken in production test. Basic issues of product quality are explained. The very fundamental test methods are explained and a detailed definition of types of faults and fault definition is given.

Chapter 2: Scan Insertion
Most widely used for testing of standard cell designs is the implementation of scan paths and generation of test patterns by ATPG. Details of scan design are explained, with focus on practical understanding of all possible issues that can occur within scan designs. Design for test rules are given. Advanced at-speed testing methods for deep submicron designs are explained. Methods for automatic-test-pattern-generation (ATPG) and pattern compaction are explained.

Chapter 3: Build-In self test
Beside scan test, build-in self tests methods have gained an important role for SOC designs, especially for memory testing. Also BIST for logic test gets more and more popular. Basics of both methods are explained. For memory BIST, memory fail mechanisms and memory BIST algorithms are explained. For implementing logic BIST, the basic structures for random signal generation and signature generators are given.

Chapter 4: Boundary Scan
For board level testing, boundary scan standards exist for almost two decades: Joint test actions group (JTAG) boundary scan standard from 1988, and the IEEE 1149.1 testability bus standard. Implementation and instructions available within these standards are explained

Chapter 5: Quality
This chapter gives a focus on quality and manufacturability. Specially the term "process capability index" is explained. What is the meaning of CPK factors and how are CPK factors calculated?

LAB exercices:

LAB1
This lab goes through all the steps of a modern design flow with scan insertion and ATPG implementation. Starting with a simple example, the tutorial session goes through all design steps of functional simulation, synthesis and scan insertion.  Faults and patterns are generated. Afterwards the generated patterns are verified by backannotation. Design examples will be a simple counter and a 5 bit flash converter.

LAB2
An implementation of a LSFR register for random stimulus generation and a MISR register for signature generation should be coded and simulated. Logic test of a design example should be implemented by usage of the generated LSFR and MISR.

LAB3
Within this lab, a simple memory BIST for RAM and ROM testing should be developed.

Within the labs, following design tools are used

• Synopsys design compiler and DFT compiler
• Synopsys Tetramax
• Mentor Modelsim

All HDL sources of the design examples are coded in VHDL, basic knowledge of VHDL is assumed.