Labs

Inverter
Two inverters, a symmetric implementation and a balanced implementation, will be considered. First, the NMOS and PMOS transistor widths of the balanced inverter have to be selected such, that the switching point is at Vdd/2. The Voltage Transfer Characteristic VTC will be studied for both inverters, as well as the propagation delay depending on the inverters load. Finally, the switching energy with a typical inverter load needs to be found and the Energy Delay Product EDP of both implementations compared.

Combinatorial Logic
An AND-gate with 2 inverted and 1 non-inverted inputs is implemented as NOR-gate with 2 non-inverted inputs and 1 inverted input. The gate is to be designed and analyzed for the propagation delay.

Dynamic CMOS Gate
A dynamic CMOS gate (OR with 4 inputs, domino logic) is to be designed. All parasitic effects like min clock, clock feed through, charge redistribution and output transitions are to be studied.

Sequential Logic
A dynamic register cell (C2MOS) using min transistor dimensions is to be designed. First the clock to Q delay as well as setup- and hold-times are to be determined. The min clock frequency for save operation is to be determined. It needs to be verified, that clock overlap will not harm (NORA logic) and the influence of longer clock transitions will be studied. This is to be done by adding a simple clock generator and varying the load on ckl and clk'.